twelveto1.tdf

一个关于VHDL的cpld开发实验程序

include "fp.inc";
subdesign twelveto1
(inclk:input;
outa[6..0]:output;
outb[6..0]:output;
)
variable
f1:fp;
va[3..0]:dff;
vb[3..0]:dff;
begin
f1.inclk=inclk;
va[3..0].clk=f1.outputf;vb[3..0].clk=f1.outputf;
if(va[]==2 and vb[]==1)then
   va[]=1;
   vb[]=0;
elsif va[]==9 then
   va[]=0;
   vb[]=vb[]+1;
else
   va[]=va[]+1;
   vb[]=vb[];
end if;
table
   va[3..0]=>outa0,outa1,outa2,outa3,outa4,outa5,outa6;
   H"0"=>1,1,1,1,1,1,0;
   H"1"=>0,1,1,0,0,0,0;
   H"2"=>1,1,0,1,1,0,1;
   H"3"=>1,1,1,1,0,0,1;
   H"4"=>0,1,1,0,0,1,1;
   H"5"=>1,0,1,1,0,1,1;
   H"6"=>1,0,1,1,1,1,1;
   H"7"=>1,1,1,0,0,0,0;
   H"8"=>1,1,1,1,1,1,1;
   H"9"=>1,1,1,1,0,1,1;
   H"A"=>1,1,1,0,1,1,1;
   H"B"=>0,0,1,1,1,1,1;
   H"C"=>1,0,0,1,1,1,0;
   H"D"=>0,1,1,1,1,0,1;
   H"E"=>1,0,0,1,1,1,1;
   H"F"=>1,0,0,0,1,1,1;
end table;
table
   vb[3..0]=>outb0,outb1,outb2,outb3,outb4,outb5,outb6;
   H"0"=>1,1,1,1,1,1,0;
   H"1"=>0,1,1,0,0,0,0;
   H"2"=>1,1,0,1,1,0,1;
   H"3"=>1,1,1,1,0,0,1;
   H"4"=>0,1,1,0,0,1,1;
   H"5"=>1,0,1,1,0,1,1;
   H"6"=>1,0,1,1,1,1,1;
   H"7"=>1,1,1,0,0,0,0;
   H"8"=>1,1,1,1,1,1,1;
   H"9"=>1,1,1,1,0,1,1;
   H"A"=>1,1,1,0,1,1,1;
   H"B"=>0,0,1,1,1,1,1;
   H"C"=>1,0,0,1,1,1,0;
   H"D"=>0,1,1,1,1,0,1;
   H"E"=>1,0,0,1,1,1,1;
   H"F"=>1,0,0,0,1,1,1;
end table;
end;