📄 fp.rpt
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-- Equation name is 'fp19', location is LC4_B11, type is buried.
fp19 = DFFE( _EQ020, GLOBAL( inclk), VCC, VCC, VCC);
_EQ020 = !fp18 & fp19 & _LC4_B10
# fp19 & _LC4_B10 & !_LC8_B11
# fp18 & !fp19 & _LC4_B10 & _LC8_B11;
-- Node name is 'fp20' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp20', location is LC5_B1, type is buried.
fp20 = DFFE( _EQ021, GLOBAL( inclk), VCC, VCC, VCC);
_EQ021 = fp20 & !_LC1_B11 & _LC4_B10
# !fp20 & _LC1_B11 & _LC4_B10;
-- Node name is 'fp21' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp21', location is LC4_B1, type is buried.
fp21 = DFFE( _EQ022, GLOBAL( inclk), VCC, VCC, VCC);
_EQ022 = !fp20 & fp21 & _LC4_B10
# fp21 & !_LC1_B11 & _LC4_B10
# fp20 & !fp21 & _LC1_B11 & _LC4_B10;
-- Node name is 'fp22' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp22', location is LC3_B4, type is buried.
fp22 = DFFE( _EQ023, GLOBAL( inclk), VCC, VCC, VCC);
_EQ023 = fp22 & !_LC2_B1 & _LC4_B10
# !fp22 & _LC2_B1 & _LC4_B10;
-- Node name is 'fp23' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp23', location is LC8_B1, type is buried.
fp23 = DFFE( _EQ024, GLOBAL( inclk), VCC, VCC, VCC);
_EQ024 = fp23 & _LC4_B10 & !_LC6_B1
# !fp23 & _LC4_B10 & _LC6_B1;
-- Node name is 'fp24' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp24', location is LC7_B1, type is buried.
fp24 = DFFE( _EQ025, GLOBAL( inclk), VCC, VCC, VCC);
_EQ025 = !fp23 & fp24 & _LC4_B10
# fp24 & _LC4_B10 & !_LC6_B1
# fp23 & !fp24 & _LC4_B10 & _LC6_B1;
-- Node name is 'outputf' from file "fp.tdf" line 16, column 1
-- Equation name is 'outputf', type is output
outputf = f;
-- Node name is '~95~1' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~1', location is LC1_B1, type is buried.
-- synthesized logic cell
_LC1_B1 = LCELL( _EQ026);
_EQ026 = !fp21
# !fp20
# !fp19
# !fp18;
-- Node name is '~95~2' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~2', location is LC3_B1, type is buried.
-- synthesized logic cell
_LC3_B1 = LCELL( _EQ027);
_EQ027 = !fp24
# fp23
# !fp22;
-- Node name is '~95~3' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~3', location is LC3_B10, type is buried.
-- synthesized logic cell
_LC3_B10 = LCELL( _EQ028);
_EQ028 = fp8
# fp7
# fp6;
-- Node name is '~95~4' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~4', location is LC3_B5, type is buried.
-- synthesized logic cell
_LC3_B5 = LCELL( _EQ029);
_EQ029 = !fp13
# !fp12
# !fp11
# fp10;
-- Node name is '~95~5' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~5', location is LC2_B11, type is buried.
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ030);
_EQ030 = fp17
# !fp16
# fp15
# !fp14;
-- Node name is '~95~6' from file "fp.tdf" line 9, column 8
-- Equation name is '~95~6', location is LC5_B10, type is buried.
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ031);
_EQ031 = fp9
# _LC3_B10
# _LC3_B5
# _LC2_B11;
-- Node name is ':95' from file "fp.tdf" line 9, column 8
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ032);
_EQ032 = _LC1_B1
# _LC3_B1
# _LC5_B10
# !_LC1_B9;
-- Node name is ':105' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ033);
_EQ033 = fp0 & fp1;
-- Node name is ':113' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC3_B9', type is buried
_LC3_B9 = LCELL( _EQ034);
_EQ034 = fp2 & fp3 & _LC2_B9;
-- Node name is ':121' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ035);
_EQ035 = fp4 & fp5 & _LC3_B9;
-- Node name is ':129' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ036);
_EQ036 = fp6 & fp7 & _LC1_B9;
-- Node name is ':137' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ037);
_EQ037 = fp8 & fp9 & _LC1_B10;
-- Node name is ':145' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ038);
_EQ038 = fp10 & fp11 & _LC2_B10;
-- Node name is ':153' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ039);
_EQ039 = fp12 & fp13 & _LC4_B5;
-- Node name is ':161' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ040);
_EQ040 = fp14 & fp15 & _LC2_B5;
-- Node name is ':169' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ041);
_EQ041 = fp16 & fp17 & _LC5_B11;
-- Node name is ':177' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ042);
_EQ042 = fp18 & fp19 & _LC8_B11;
-- Node name is ':185' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ043);
_EQ043 = fp20 & fp21 & _LC1_B11;
-- Node name is ':189' from file "fp.tdf" line 13, column 13
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ044);
_EQ044 = fp20 & fp21 & fp22 & _LC1_B11;
Project Information g:\cpld_example\twelveto1\fp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,962K
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