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📄 fp.rpt

📁 一个关于VHDL的cpld开发实验程序
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Device-Specific Information:                  g:\cpld_example\twelveto1\fp.rpt
fp

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      2     -    B    04       DFFE   +            0    1    1    0  f
   -      2     -    B    12       DFFE   +            0    0    0    2  fp0
   -      4     -    B    09       DFFE   +            0    2    0    1  fp1
   -      5     -    B    09       DFFE   +            0    2    0    2  fp2
   -      6     -    B    09       DFFE   +            0    3    0    1  fp3
   -      7     -    B    09       DFFE   +            0    2    0    2  fp4
   -      8     -    B    09       DFFE   +            0    3    0    1  fp5
   -      8     -    B    04       DFFE   +            0    2    0    3  fp6
   -      7     -    B    10       DFFE   +            0    3    0    2  fp7
   -      6     -    B    10       DFFE   +            0    2    0    3  fp8
   -      8     -    B    10       DFFE   +            0    3    0    2  fp9
   -      8     -    B    05       DFFE   +            0    2    0    3  fp10
   -      7     -    B    05       DFFE   +            0    3    0    2  fp11
   -      6     -    B    05       DFFE   +            0    2    0    3  fp12
   -      5     -    B    05       DFFE   +            0    3    0    2  fp13
   -      1     -    B    04       DFFE   +            0    2    0    3  fp14
   -      1     -    B    05       DFFE   +            0    3    0    2  fp15
   -      7     -    B    11       DFFE   +            0    2    0    3  fp16
   -      6     -    B    11       DFFE   +            0    3    0    2  fp17
   -      3     -    B    11       DFFE   +            0    2    0    3  fp18
   -      4     -    B    11       DFFE   +            0    3    0    2  fp19
   -      5     -    B    01       DFFE   +            0    2    0    4  fp20
   -      4     -    B    01       DFFE   +            0    3    0    3  fp21
   -      3     -    B    04       DFFE   +            0    2    0    2  fp22
   -      8     -    B    01       DFFE   +            0    2    0    2  fp23
   -      7     -    B    01       DFFE   +            0    3    0    1  fp24
   -      1     -    B    01        OR2    s           0    4    0    1  ~95~1
   -      3     -    B    01        OR2    s           0    3    0    1  ~95~2
   -      3     -    B    10        OR2    s           0    3    0    1  ~95~3
   -      3     -    B    05        OR2    s           0    4    0    1  ~95~4
   -      2     -    B    11        OR2    s           0    4    0    1  ~95~5
   -      5     -    B    10        OR2    s           0    4    0    1  ~95~6
   -      4     -    B    10        OR2                0    4    0   25  :95
   -      2     -    B    09       AND2                0    2    0    3  :105
   -      3     -    B    09       AND2                0    3    0    3  :113
   -      1     -    B    09       AND2                0    3    0    4  :121
   -      1     -    B    10       AND2                0    3    0    3  :129
   -      2     -    B    10       AND2                0    3    0    3  :137
   -      4     -    B    05       AND2                0    3    0    3  :145
   -      2     -    B    05       AND2                0    3    0    3  :153
   -      5     -    B    11       AND2                0    3    0    3  :161
   -      8     -    B    11       AND2                0    3    0    3  :169
   -      1     -    B    11       AND2                0    3    0    4  :177
   -      2     -    B    01       AND2                0    3    0    1  :185
   -      6     -    B    01       AND2                0    4    0    2  :189


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                  g:\cpld_example\twelveto1\fp.rpt
fp

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:      17/ 96( 17%)     2/ 48(  4%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                  g:\cpld_example\twelveto1\fp.rpt
fp

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       26         inclk


Device-Specific Information:                  g:\cpld_example\twelveto1\fp.rpt
fp

** EQUATIONS **

inclk    : INPUT;

-- Node name is 'f' from file "fp.tdf" line 6, column 1
-- Equation name is 'f', location is LC2_B4, type is buried.
f        = DFFE( _EQ001, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ001 = !f & !_LC4_B10
         #  f &  _LC4_B10;

-- Node name is 'fp0' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp0', location is LC2_B12, type is buried.
fp0      = DFFE(!fp0, GLOBAL( inclk),  VCC,  VCC,  VCC);

-- Node name is 'fp1' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp1', location is LC4_B9, type is buried.
fp1      = DFFE( _EQ002, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ002 =  fp0 & !fp1 &  _LC4_B10
         # !fp0 &  fp1 &  _LC4_B10;

-- Node name is 'fp2' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp2', location is LC5_B9, type is buried.
fp2      = DFFE( _EQ003, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ003 =  fp2 & !_LC2_B9 &  _LC4_B10
         # !fp2 &  _LC2_B9 &  _LC4_B10;

-- Node name is 'fp3' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp3', location is LC6_B9, type is buried.
fp3      = DFFE( _EQ004, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ004 = !fp2 &  fp3 &  _LC4_B10
         #  fp3 & !_LC2_B9 &  _LC4_B10
         #  fp2 & !fp3 &  _LC2_B9 &  _LC4_B10;

-- Node name is 'fp4' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp4', location is LC7_B9, type is buried.
fp4      = DFFE( _EQ005, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ005 =  fp4 & !_LC3_B9 &  _LC4_B10
         # !fp4 &  _LC3_B9 &  _LC4_B10;

-- Node name is 'fp5' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp5', location is LC8_B9, type is buried.
fp5      = DFFE( _EQ006, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ006 = !fp4 &  fp5 &  _LC4_B10
         #  fp5 & !_LC3_B9 &  _LC4_B10
         #  fp4 & !fp5 &  _LC3_B9 &  _LC4_B10;

-- Node name is 'fp6' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp6', location is LC8_B4, type is buried.
fp6      = DFFE( _EQ007, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ007 =  fp6 & !_LC1_B9 &  _LC4_B10
         # !fp6 &  _LC1_B9 &  _LC4_B10;

-- Node name is 'fp7' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp7', location is LC7_B10, type is buried.
fp7      = DFFE( _EQ008, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ008 = !fp6 &  fp7 &  _LC4_B10
         #  fp7 & !_LC1_B9 &  _LC4_B10
         #  fp6 & !fp7 &  _LC1_B9 &  _LC4_B10;

-- Node name is 'fp8' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp8', location is LC6_B10, type is buried.
fp8      = DFFE( _EQ009, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ009 =  fp8 & !_LC1_B10 &  _LC4_B10
         # !fp8 &  _LC1_B10 &  _LC4_B10;

-- Node name is 'fp9' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp9', location is LC8_B10, type is buried.
fp9      = DFFE( _EQ010, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ010 = !fp8 &  fp9 &  _LC4_B10
         #  fp9 & !_LC1_B10 &  _LC4_B10
         #  fp8 & !fp9 &  _LC1_B10 &  _LC4_B10;

-- Node name is 'fp10' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp10', location is LC8_B5, type is buried.
fp10     = DFFE( _EQ011, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ011 =  fp10 & !_LC2_B10 &  _LC4_B10
         # !fp10 &  _LC2_B10 &  _LC4_B10;

-- Node name is 'fp11' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp11', location is LC7_B5, type is buried.
fp11     = DFFE( _EQ012, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ012 = !fp10 &  fp11 &  _LC4_B10
         #  fp11 & !_LC2_B10 &  _LC4_B10
         #  fp10 & !fp11 &  _LC2_B10 &  _LC4_B10;

-- Node name is 'fp12' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp12', location is LC6_B5, type is buried.
fp12     = DFFE( _EQ013, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ013 =  fp12 & !_LC4_B5 &  _LC4_B10
         # !fp12 &  _LC4_B5 &  _LC4_B10;

-- Node name is 'fp13' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp13', location is LC5_B5, type is buried.
fp13     = DFFE( _EQ014, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ014 = !fp12 &  fp13 &  _LC4_B10
         #  fp13 & !_LC4_B5 &  _LC4_B10
         #  fp12 & !fp13 &  _LC4_B5 &  _LC4_B10;

-- Node name is 'fp14' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp14', location is LC1_B4, type is buried.
fp14     = DFFE( _EQ015, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ015 =  fp14 & !_LC2_B5 &  _LC4_B10
         # !fp14 &  _LC2_B5 &  _LC4_B10;

-- Node name is 'fp15' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp15', location is LC1_B5, type is buried.
fp15     = DFFE( _EQ016, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ016 = !fp14 &  fp15 &  _LC4_B10
         #  fp15 & !_LC2_B5 &  _LC4_B10
         #  fp14 & !fp15 &  _LC2_B5 &  _LC4_B10;

-- Node name is 'fp16' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp16', location is LC7_B11, type is buried.
fp16     = DFFE( _EQ017, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ017 =  fp16 &  _LC4_B10 & !_LC5_B11
         # !fp16 &  _LC4_B10 &  _LC5_B11;

-- Node name is 'fp17' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp17', location is LC6_B11, type is buried.
fp17     = DFFE( _EQ018, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ018 = !fp16 &  fp17 &  _LC4_B10
         #  fp17 &  _LC4_B10 & !_LC5_B11
         #  fp16 & !fp17 &  _LC4_B10 &  _LC5_B11;

-- Node name is 'fp18' from file "fp.tdf" line 5, column 3
-- Equation name is 'fp18', location is LC3_B11, type is buried.
fp18     = DFFE( _EQ019, GLOBAL( inclk),  VCC,  VCC,  VCC);
  _EQ019 =  fp18 &  _LC4_B10 & !_LC8_B11
         # !fp18 &  _LC4_B10 &  _LC8_B11;

-- Node name is 'fp19' from file "fp.tdf" line 5, column 3

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