twelveto1v.rpt

一个关于VHDL的cpld开发实验程序

         # !sa0 &  sa3;

-- Node name is ':756' 
-- Equation name is '_LC4_J16', type is buried 
_LC4_J16 = LCELL( _EQ069);
  _EQ069 = !sa0
         # !sa2
         # !sa1 & !sa3
         #  sa1 &  sa3;

-- Node name is '~760~1' 
-- Equation name is '~760~1', location is LC3_J18, type is buried.
-- synthesized logic cell 
_LC3_J18 = LCELL( _EQ070);
  _EQ070 =  sa0 & !sa1 &  sa2 & !sa3
         # !sa0 &  sa1 &  sa2 & !sa3;

-- Node name is '~771~1' 
-- Equation name is '~771~1', location is LC2_J18, type is buried.
-- synthesized logic cell 
_LC2_J18 = LCELL( _EQ071);
  _EQ071 =  sa2
         #  sa3
         # !sa0 & !sa1;

-- Node name is ':771' 
-- Equation name is '_LC8_J16', type is buried 
_LC8_J16 = LCELL( _EQ072);
  _EQ072 =  _LC2_J18 &  _LC3_J18
         #  _LC2_J18 &  _LC3_J16
         #  _LC2_J18 &  _LC4_J16;

-- Node name is ':819' 
-- Equation name is '_LC8_J18', type is buried 
_LC8_J18 = LCELL( _EQ073);
  _EQ073 = !sa1 &  sa2 & !sa3
         #  sa1 & !sa2
         # !sa2 &  sa3
         #  sa0 & !sa1 &  sa2
         #  sa1 &  sa3
         # !sa0 &  sa1;

-- Node name is ':961' 
-- Equation name is '_LC5_E19', type is buried 
_LC5_E19 = LCELL( _EQ074);
  _EQ074 = !sb0 & !sb1 &  sb2 & !sb3;

-- Node name is ':997' 
-- Equation name is '_LC1_E19', type is buried 
!_LC1_E19 = _LC1_E19~NOT;
_LC1_E19~NOT = LCELL( _EQ075);
  _EQ075 =  sb3
         #  sb2
         #  sb1
         # !sb0;

-- Node name is ':1002' 
-- Equation name is '_LC8_E19', type is buried 
_LC8_E19 = LCELL( _EQ076);
  _EQ076 =  sb1 &  sb2
         # !sb0 &  sb1
         #  sb1 & !sb3
         # !sb0 & !sb2
         # !sb0 &  sb3
         # !sb1 & !sb2 &  sb3
         #  sb0 &  sb2 & !sb3;

-- Node name is ':1023' 
-- Equation name is '_LC4_E19', type is buried 
_LC4_E19 = LCELL( _EQ077);
  _EQ077 = !sb3
         #  sb0 & !sb1
         # !sb1 & !sb2
         # !sb0 & !sb2;

-- Node name is ':1041' 
-- Equation name is '_LC4_E21', type is buried 
_LC4_E21 = LCELL( _EQ078);
  _EQ078 = !_LC3_E21 &  _LC7_E21
         # !_LC3_E21 &  _LC4_E19;

-- Node name is ':1048' 
-- Equation name is '_LC3_E19', type is buried 
_LC3_E19 = LCELL( _EQ079);
  _EQ079 =  _LC4_E21
         #  _LC6_E19
         #  _LC1_E19
         #  _LC5_E19;

-- Node name is '~1090~1' 
-- Equation name is '~1090~1', location is LC2_E21, type is buried.
-- synthesized logic cell 
_LC2_E21 = LCELL( _EQ080);
  _EQ080 =  _LC3_E21
         #  _LC5_E19;

-- Node name is '~1090~2' 
-- Equation name is '~1090~2', location is LC7_E21, type is buried.
-- synthesized logic cell 
_LC7_E21 = LCELL( _EQ081);
  _EQ081 =  sb0 &  sb1 &  sb2 & !sb3
         # !sb1 & !sb2 &  sb3
         # !sb0 & !sb2 &  sb3;

-- Node name is ':1096' 
-- Equation name is '_LC2_E22', type is buried 
_LC2_E22 = LCELL( _EQ082);
  _EQ082 =  sb0 & !sb1
         # !sb1 & !sb2
         #  sb0 & !sb2
         # !sb2 &  sb3
         # !sb1 & !sb3
         #  sb0 & !sb3
         #  sb2 & !sb3;

-- Node name is ':1131' 
-- Equation name is '_LC5_E21', type is buried 
_LC5_E21 = LCELL( _EQ083);
  _EQ083 = !sb1
         # !sb0 &  sb2
         #  sb0 & !sb2
         # !sb0 & !sb3
         # !sb2 & !sb3;

-- Node name is ':1140' 
-- Equation name is '_LC6_E21', type is buried 
_LC6_E21 = LCELL( _EQ084);
  _EQ084 = !_LC5_E19 &  _LC5_E21
         #  _LC3_E21 & !_LC5_E19;

-- Node name is ':1146' 
-- Equation name is '_LC8_E21', type is buried 
_LC8_E21 = LCELL( _EQ085);
  _EQ085 = !_LC1_E19 &  _LC6_E21
         # !_LC1_E19 &  _LC6_E19;

-- Node name is ':1194' 
-- Equation name is '_LC1_E22', type is buried 
_LC1_E22 = LCELL( _EQ086);
  _EQ086 =  sb1 &  sb3
         #  sb2 &  sb3
         # !sb0 &  sb1
         # !sb0 & !sb2
         # !sb0 &  sb3;

-- Node name is ':1227' 
-- Equation name is '_LC2_E19', type is buried 
_LC2_E19 = LCELL( _EQ087);
  _EQ087 = !sb0
         # !sb2
         # !sb1 & !sb3
         #  sb1 &  sb3;

-- Node name is '~1231~1' 
-- Equation name is '~1231~1', location is LC3_E21, type is buried.
-- synthesized logic cell 
_LC3_E21 = LCELL( _EQ088);
  _EQ088 =  sb0 & !sb1 &  sb2 & !sb3
         # !sb0 &  sb1 &  sb2 & !sb3;

-- Node name is ':1242' 
-- Equation name is '_LC4_E24', type is buried 
_LC4_E24 = LCELL( _EQ089);
  _EQ089 = !_LC1_E19 &  _LC2_E19 & !_LC6_E19
         # !_LC1_E19 &  _LC2_E21 & !_LC6_E19;

-- Node name is ':1275' 
-- Equation name is '_LC7_E19', type is buried 
_LC7_E19 = LCELL( _EQ090);
  _EQ090 = !sb2 &  sb3
         #  sb0 &  sb3
         #  sb1 &  sb3;

-- Node name is '~1285~1' 
-- Equation name is '~1285~1', location is LC6_E19, type is buried.
-- synthesized logic cell 
_LC6_E19 = LCELL( _EQ091);
  _EQ091 =  sb1 & !sb2 & !sb3;

-- Node name is ':1290' 
-- Equation name is '_LC1_E24', type is buried 
_LC1_E24 = LCELL( _EQ092);
  _EQ092 = !_LC1_E19 &  _LC6_E19
         # !_LC1_E19 &  _LC2_E21
         # !_LC1_E19 &  _LC7_E19;



Project Information                   g:\cpld_example\twelveto1\twelveto1v.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00: