📄 twelveto1v.rpt
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Synthesized logic cells: 14/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 1 0 0 0 0 0 8 0 8 8 0 8 0 0 0 0 0 49/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 8 0 0 0 0 0 0 0 0 0 1 2 1 0 5 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 0 0 0 0 0 0 0 0 1 2 1 0 5 0 8 8 0 8 2 0 2 0 8 0 0 0 0 8 0 0 0 0 0 1 0 0 0 0 0 8 0 8 8 0 8 0 0 0 0 0 94/0
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G ^ 0 0 0 0 finclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
168 - - - 17 OUTPUT 0 1 0 0 outputa0
167 - - - 16 OUTPUT 0 1 0 0 outputa1
166 - - - 15 OUTPUT 0 1 0 0 outputa2
164 - - - 14 OUTPUT 0 1 0 0 outputa3
163 - - - 14 OUTPUT 0 1 0 0 outputa4
162 - - - 13 OUTPUT 0 1 0 0 outputa5
161 - - - 12 OUTPUT 0 1 0 0 outputa6
177 - - - 24 OUTPUT 0 1 0 0 outputb0
176 - - - 23 OUTPUT 0 1 0 0 outputb1
175 - - - 22 OUTPUT 0 1 0 0 outputb2
174 - - - 22 OUTPUT 0 1 0 0 outputb3
173 - - - 21 OUTPUT 0 1 0 0 outputb4
172 - - - 20 OUTPUT 0 1 0 0 outputb5
170 - - - 19 OUTPUT 0 1 0 0 outputb6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 26 DFFE + 0 1 0 8 |fp:u1|f
- 2 - A 36 DFFE + 0 0 0 3 |fp:u1|fp0
- 4 - A 47 DFFE + 0 2 0 2 |fp:u1|fp1
- 5 - A 47 DFFE + 0 3 0 1 |fp:u1|fp2
- 6 - A 47 DFFE + 0 2 0 1 |fp:u1|fp3
- 7 - A 47 DFFE + 0 2 0 2 |fp:u1|fp4
- 8 - A 47 DFFE + 0 3 0 1 |fp:u1|fp5
- 3 - A 42 DFFE + 0 2 0 2 |fp:u1|fp6
- 1 - A 42 DFFE + 0 2 0 3 |fp:u1|fp7
- 6 - A 42 DFFE + 0 3 0 2 |fp:u1|fp8
- 4 - A 42 DFFE + 0 2 0 3 |fp:u1|fp9
- 8 - A 42 DFFE + 0 3 0 2 |fp:u1|fp10
- 5 - A 26 DFFE + 0 2 0 3 |fp:u1|fp11
- 6 - A 44 DFFE + 0 3 0 2 |fp:u1|fp12
- 8 - A 44 DFFE + 0 2 0 3 |fp:u1|fp13
- 7 - A 44 DFFE + 0 3 0 2 |fp:u1|fp14
- 7 - A 26 DFFE + 0 2 0 4 |fp:u1|fp15
- 6 - A 26 DFFE + 0 3 0 3 |fp:u1|fp16
- 8 - A 30 DFFE + 0 2 0 2 |fp:u1|fp17
- 7 - A 30 DFFE + 0 2 0 4 |fp:u1|fp18
- 6 - A 30 DFFE + 0 3 0 3 |fp:u1|fp19
- 5 - A 30 DFFE + 0 2 0 2 |fp:u1|fp20
- 8 - A 45 DFFE + 0 2 0 3 |fp:u1|fp21
- 7 - A 45 DFFE + 0 3 0 2 |fp:u1|fp22
- 6 - A 45 DFFE + 0 2 0 2 |fp:u1|fp23
- 5 - A 45 DFFE + 0 3 0 1 |fp:u1|fp24
- 1 - A 30 OR2 s 0 4 0 1 |fp:u1|~95~1
- 3 - A 45 OR2 s 0 3 0 1 |fp:u1|~95~2
- 2 - A 45 OR2 s 0 3 0 1 |fp:u1|~95~3
- 1 - A 44 OR2 s 0 4 0 1 |fp:u1|~95~4
- 4 - A 44 OR2 s 0 4 0 1 |fp:u1|~95~5
- 2 - A 44 OR2 s 0 4 0 1 |fp:u1|~95~6
- 1 - A 45 OR2 0 4 0 25 |fp:u1|:95
- 1 - A 47 AND2 0 3 0 2 |fp:u1|:109
- 3 - A 47 AND2 0 2 0 3 |fp:u1|:113
- 2 - A 47 AND2 0 3 0 3 |fp:u1|:121
- 2 - A 42 AND2 0 2 0 3 |fp:u1|:125
- 7 - A 42 AND2 0 3 0 3 |fp:u1|:133
- 5 - A 42 AND2 0 3 0 3 |fp:u1|:141
- 5 - A 44 AND2 0 3 0 3 |fp:u1|:149
- 3 - A 44 AND2 0 3 0 4 |fp:u1|:157
- 2 - A 26 AND2 0 3 0 1 |fp:u1|:165
- 3 - A 30 AND2 0 4 0 4 |fp:u1|:169
- 4 - A 30 AND2 0 3 0 1 |fp:u1|:177
- 2 - A 30 AND2 0 4 0 3 |fp:u1|:181
- 4 - A 45 AND2 0 3 0 2 |fp:u1|:189
- 6 - J 02 AND2 0 2 0 1 |LPM_ADD_SUB:121|addcore:adder|:55
- 1 - E 21 AND2 0 3 0 1 |LPM_ADD_SUB:121|addcore:adder|:59
- 8 - J 02 AND2 0 2 0 1 |LPM_ADD_SUB:146|addcore:adder|:55
- 5 - J 02 DFFE 0 4 0 13 sa3 (:17)
- 4 - J 02 DFFE 0 4 0 14 sa2 (:18)
- 2 - J 02 DFFE 0 3 0 15 sa1 (:19)
- 3 - J 02 DFFE 0 1 0 16 sa0 (:20)
- 3 - A 26 DFFE 0 4 0 12 sb3 (:21)
- 1 - J 02 DFFE 0 4 0 13 sb2 (:22)
- 4 - A 26 DFFE 0 4 0 14 sb1 (:23)
- 1 - A 26 DFFE 0 3 0 14 sb0 (:24)
- 4 - J 18 OR2 ! 0 2 0 5 :74
- 1 - J 16 AND2 0 4 0 5 :100
- 7 - J 02 AND2 s 0 2 0 3 ~228~1
- 3 - J 16 AND2 0 4 0 2 :490
- 5 - J 18 OR2 ! 0 4 0 1 :514
- 2 - J 12 OR2 0 4 1 0 :531
- 7 - J 18 OR2 0 4 0 1 :552
- 1 - J 18 OR2 0 3 0 1 :570
- 2 - J 14 OR2 0 3 1 0 :577
- 6 - J 18 OR2 s 0 4 0 1 ~619~1
- 4 - J 13 OR2 0 4 1 0 :625
- 1 - J 13 OR2 0 4 1 0 :675
- 2 - J 16 OR2 0 4 1 0 :723
- 4 - J 16 OR2 0 4 0 1 :756
- 3 - J 18 OR2 s 0 4 0 2 ~760~1
- 2 - J 18 OR2 s 0 4 0 2 ~771~1
- 8 - J 16 OR2 0 4 1 0 :771
- 8 - J 18 OR2 0 4 1 0 :819
- 5 - E 19 AND2 0 4 0 3 :961
- 1 - E 19 OR2 ! 0 4 0 5 :997
- 8 - E 19 OR2 0 4 1 0 :1002
- 4 - E 19 OR2 0 4 0 1 :1023
- 4 - E 21 OR2 0 3 0 1 :1041
- 3 - E 19 OR2 0 4 1 0 :1048
- 2 - E 21 OR2 s 0 2 0 2 ~1090~1
- 7 - E 21 OR2 s 0 4 0 1 ~1090~2
- 2 - E 22 OR2 0 4 1 0 :1096
- 5 - E 21 OR2 0 4 0 1 :1131
- 6 - E 21 OR2 0 3 0 1 :1140
- 8 - E 21 OR2 0 3 1 0 :1146
- 1 - E 22 OR2 0 4 1 0 :1194
- 2 - E 19 OR2 0 4 0 1 :1227
- 3 - E 21 OR2 s 0 4 0 3 ~1231~1
- 4 - E 24 OR2 0 4 1 0 :1242
- 7 - E 19 OR2 0 4 0 1 :1275
- 6 - E 19 AND2 s 0 3 0 4 ~1285~1
- 1 - E 24 OR2 0 4 1 0 :1290
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 21/208( 10%) 1/104( 0%) 1/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 3/208( 1%) 9/104( 8%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 9/208( 4%) 5/104( 4%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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