📄 twelveto1v.rpt
字号:
Project Information g:\cpld_example\twelveto1\twelveto1v.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 08/06/2004 16:21:14
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
TWELVETO1V
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
twelveto1v
EP1K100QC208-3 1 14 0 0 0 % 94 1 %
User Pins: 1 14 0
Project Information g:\cpld_example\twelveto1\twelveto1v.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K100QC208-3 are preliminary
Project Information g:\cpld_example\twelveto1\twelveto1v.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
twelveto1v@183 finclk
twelveto1v@168 outputa0
twelveto1v@167 outputa1
twelveto1v@166 outputa2
twelveto1v@164 outputa3
twelveto1v@163 outputa4
twelveto1v@162 outputa5
twelveto1v@161 outputa6
twelveto1v@177 outputb0
twelveto1v@176 outputb1
twelveto1v@175 outputb2
twelveto1v@174 outputb3
twelveto1v@173 outputb4
twelveto1v@172 outputb5
twelveto1v@170 outputb6
Project Information g:\cpld_example\twelveto1\twelveto1v.rpt
** FILE HIERARCHY **
|lpm_add_sub:121|
|lpm_add_sub:121|addcore:adder|
|lpm_add_sub:121|altshift:result_ext_latency_ffs|
|lpm_add_sub:121|altshift:carry_ext_latency_ffs|
|lpm_add_sub:121|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:146|
|lpm_add_sub:146|addcore:adder|
|lpm_add_sub:146|altshift:result_ext_latency_ffs|
|lpm_add_sub:146|altshift:carry_ext_latency_ffs|
|lpm_add_sub:146|altshift:oflow_ext_latency_ffs|
|fp:u1|
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
***** Logic for device 'twelveto1v' compiled without errors.
Device: EP1K100QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R o o o o o o o R o o o o o o o R R R R
E E E E E E E E E E E E E E E E E E E E E E u u u u u u u E u u u u u u u E E E E
S S S S S S S V S S S S S S S S S S S S S V f S S t t t t t t t S t t t t t t t S S S S
E E E E E E E C E E E E E E V E E E E E E E C i E E V p p p p p p p E p p p V p p p p E E E E
R R R R R R R C R R R R R R C R R R R R R R C n R R C u u u u u u u R u u u C u u u u R R R R
V V V V V V V I V V V V V V C V V V V V G V V I G c G G V V C t t t t t t G t V t t t C t t t t V V V V
E E E E E E E N E E E E E E I E E E E E N E E N N l N N E E I b b b b b b N b E a a a I a a a a E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D k D D D D O 0 1 2 3 4 5 D 6 D 0 1 2 O 3 4 5 6 D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K100QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R R G V G G G G G R V R R R R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E E E E E E C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C D D D D D S C S S S S S S C S S S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E E I E I E E E E E E I E E E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R R N R O R R R R R R N R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V V T V V V V V V V T V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1v.rpt
twelveto1v
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A26 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 2/2 0/2 6/26( 23%)
A30 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/26( 19%)
A36 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/26( 0%)
A42 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 2/26( 7%)
A44 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 9/26( 34%)
A45 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/26( 23%)
A47 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/26( 7%)
E19 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 0/2 0/2 5/26( 19%)
E21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/26( 30%)
E22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
E24 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/26( 19%)
J2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/26( 19%)
J12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
J13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
J14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/26( 11%)
J16 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 6/26( 23%)
J18 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 5/26( 19%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 14/141 ( 9%)
Total logic cells used: 94/4992 ( 1%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.40/4 ( 85%)
Total fan-in: 320/19968 ( 1%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 94
Total flipflops required: 34
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -