logic_74164.fit

一个关于VHDL的cpld开发实验程序

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 11/18/2004 15:11:30      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "logic_74164"
BEGIN

    DEVICE = "EP1K100QC208-3";

    "A"                            : INPUT_PIN  = 103    ;
    "B"                            : INPUT_PIN  = 104    ;
    "CLK"                          : INPUT_PIN  = 80     ;
    "Q0"                           : OUTPUT_PIN = 111    ;
    "Q1"                           : OUTPUT_PIN = 112    ;
    "Q2"                           : OUTPUT_PIN = 113    ;
    "Q3"                           : OUTPUT_PIN = 114    ;
    "Q4"                           : OUTPUT_PIN = 115    ;
    "Q5"                           : OUTPUT_PIN = 116    ;
    "Q6"                           : OUTPUT_PIN = 119    ;
    "Q7"                           : OUTPUT_PIN = 120    ;
    "|74164:1|:3"                  : LOCATION   = LC8_L26;  -- |74164:1|QA
    "|74164:1|:4"                  : LOCATION   = LC4_L11;  -- |74164:1|QB
    "|74164:1|:5"                  : LOCATION   = LC5_L11;  -- |74164:1|QC
    "|74164:1|:6"                  : LOCATION   = LC1_K15;  -- |74164:1|QD
    "|74164:1|:7"                  : LOCATION   = LC5_K15;  -- |74164:1|QE
    "|74164:1|:8"                  : LOCATION   = LC5_J19;  -- |74164:1|QF
    "|74164:1|:9"                  : LOCATION   = LC5_H3 ;  -- |74164:1|QG
    "|74164:1|:10"                 : LOCATION   = LC1_H3 ;  -- |74164:1|QH

END;

INTERNAL_INFO "logic_74164"
BEGIN
	DEVICE = EP1K100QC208-3;
    OV3C1P103 : LORAX = "1:V18C1,HHL52R11,PA21R11C25->LC8_L26|";
    OV3C0P104 : LORAX = "1:V18C0,HHL65R11,PA22R11C25->LC8_L26|";
    OD3P80  : LORAX = "1:FB3->LC8_L26,->LC4_L11,->LC5_L11,->LC1_K15,->LC5_K15,->LC5_J19,->LC5_H3,->LC1_H3|";
    LC8_L26 : LORAX = "1:MSW4R11C24,HHL103R11->OH12R11P111|2:PA12R11C10->LC4_L11||";
    LC4_L11 : LORAX = "1:MSW3R11C10,HHL30R11->OH11R11P112|";
    LC5_L11 : LORAX = "1:MSW4R11C10,V14C10|2:G206R10,PA4R10C14->LC1_K15|,2:HHL103R10->OH12R10P113||";
    LC1_K15 : LORAX = "1:MSW0R10C14,HHL47R10->OH8R10P114|";
    LC5_K15 : LORAX = "1:MSW4R10C14,V12C14|2:G203R9,PA7R9C18->LC5_J19|,2:HHL96R9->OH12R9P115||";
    LC5_J19 : LORAX = "1:MSW4R9C18,V12C18|2:G178R7,PA4R7C2->LC5_H3|,2:HHL82R8->OH12R8P116||";
    LC5_H3  : LORAX = "1:MSW4R7C2,HHL74R7->OH12R7P119|";
    LC1_H3  : LORAX = "1:MSW0R7C2,HHL44R7->OH8R7P120|";
	LC8_L26 : LORAX2 = "X, X, OV3C0P104, OV3C1P103";
	LC4_L11 : LORAX2 = "X, X, X, LC8_L26";
	LC5_L11 : LORAX2 = "X, X, X, LC4_L11";
	LC1_K15 : LORAX2 = "X, X, X, LC5_L11";
	LC5_K15 : LORAX2 = "X, X, X, LC1_K15";
	LC5_J19 : LORAX2 = "X, X, X, LC5_K15";
	LC5_H3  : LORAX2 = "X, X, X, LC5_J19";
	LC1_H3  : LORAX2 = "X, X, X, LC5_H3";
END;