📄 logic_74164.rpt
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Device-Specific Information: g:\khf-5 example\exa02\exa02\logic_74164.rpt
logic_74164
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: g:\khf-5 example\exa02\exa02\logic_74164.rpt
logic_74164
** EQUATIONS **
A : INPUT;
B : INPUT;
CLK : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC8_L26;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC4_L11;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC5_L11;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC1_K15;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC5_K15;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC5_J19;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC5_H3;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = _LC1_H3;
-- Node name is '|74164:1|:3' = '|74164:1|QA'
-- Equation name is '_LC8_L26', type is buried
_LC8_L26 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = A & B;
-- Node name is '|74164:1|:4' = '|74164:1|QB'
-- Equation name is '_LC4_L11', type is buried
_LC4_L11 = DFFE( _LC8_L26, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:5' = '|74164:1|QC'
-- Equation name is '_LC5_L11', type is buried
_LC5_L11 = DFFE( _LC4_L11, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:6' = '|74164:1|QD'
-- Equation name is '_LC1_K15', type is buried
_LC1_K15 = DFFE( _LC5_L11, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:7' = '|74164:1|QE'
-- Equation name is '_LC5_K15', type is buried
_LC5_K15 = DFFE( _LC1_K15, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:8' = '|74164:1|QF'
-- Equation name is '_LC5_J19', type is buried
_LC5_J19 = DFFE( _LC5_K15, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:9' = '|74164:1|QG'
-- Equation name is '_LC5_H3', type is buried
_LC5_H3 = DFFE( _LC5_J19, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|74164:1|:10' = '|74164:1|QH'
-- Equation name is '_LC1_H3', type is buried
_LC1_H3 = DFFE( _LC5_H3, GLOBAL( CLK), VCC, VCC, VCC);
Project Information g:\khf-5 example\exa02\exa02\logic_74164.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 50,640K
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