logic_7448.rpt

一个关于VHDL的cpld开发实验程序

43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
45:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
46:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
47:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
48:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
49:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
50:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
51:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:      g:\cpld_example\simple_logic2\logic_7448.rpt
logic_7448

** EQUATIONS **

D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;

-- Node name is 'Q0' 
-- Equation name is 'Q0', type is output 
Q0       =  _LC1_L12;

-- Node name is 'Q1' 
-- Equation name is 'Q1', type is output 
Q1       =  _LC1_L13;

-- Node name is 'Q2' 
-- Equation name is 'Q2', type is output 
Q2       =  _LC6_L13;

-- Node name is 'Q3' 
-- Equation name is 'Q3', type is output 
Q3       =  _LC4_L13;

-- Node name is 'Q4' 
-- Equation name is 'Q4', type is output 
Q4       =  _LC4_L16;

-- Node name is 'Q5' 
-- Equation name is 'Q5', type is output 
Q5       =  _LC1_L16;

-- Node name is 'Q6' 
-- Equation name is 'Q6', type is output 
Q6       =  _LC4_L18;

-- Node name is '|7448:1|:69' = '|7448:1|OA' 
-- Equation name is '_LC1_L12', type is buried 
_LC1_L12 = LCELL( _EQ001);
  _EQ001 =  D0 &  D2 & !D3
         #  D1 & !D2 & !D3
         #  D0 &  D1 & !D3
         # !D0 & !D2 & !D3
         #  D0 & !D1 &  D2
         # !D0 & !D1 & !D2
         # !D1 & !D2 &  D3
         #  D0 & !D1 &  D3;

-- Node name is '|7448:1|:68' = '|7448:1|OB' 
-- Equation name is '_LC1_L13', type is buried 
_LC1_L13 = LCELL( _EQ002);
  _EQ002 = !D0 & !D1
         #  D0 &  D1 & !D3
         # !D2 & !D3
         # !D1 & !D2;

-- Node name is '|7448:1|:70' = '|7448:1|OC' 
-- Equation name is '_LC6_L13', type is buried 
_LC6_L13 = LCELL( _EQ003);
  _EQ003 =  D2 & !D3
         #  D0 & !D3
         #  D0 & !D2
         # !D1 & !D3
         # !D1 & !D2;

-- Node name is '|7448:1|:67' = '|7448:1|OD' 
-- Equation name is '_LC4_L13', type is buried 
_LC4_L13 = LCELL( _EQ004);
  _EQ004 = !D0 &  D1
         #  D0 & !D1 &  D2
         #  D1 & !D2
         # !D0 & !D2;

-- Node name is '|7448:1|:71' = '|7448:1|OE' 
-- Equation name is '_LC4_L16', type is buried 
_LC4_L16 = LCELL( _EQ005);
  _EQ005 = !D0 & !D2
         # !D0 &  D1;

-- Node name is '|7448:1|:66' = '|7448:1|OF' 
-- Equation name is '_LC1_L16', type is buried 
_LC1_L16 = LCELL( _EQ006);
  _EQ006 = !D1 &  D3
         # !D0 & !D1
         # !D0 &  D2
         # !D1 &  D2;

-- Node name is '|7448:1|:72' = '|7448:1|OG' 
-- Equation name is '_LC4_L18', type is buried 
_LC4_L18 = LCELL( _EQ007);
  _EQ007 = !D0 &  D2
         # !D1 &  D2
         # !D0 &  D1
         #  D1 & !D2
         # !D0 &  D3
         # !D1 &  D3
         # !D2 &  D3;



Project Information               g:\cpld_example\simple_logic2\logic_7448.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:09


Memory Allocated
-----------------

Peak memory allocated during compilation  = 49,655K