logic_encoder.fit

一个关于VHDL的cpld开发实验程序

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 11/11/2004 09:34:49      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "logic_encoder"
BEGIN

    DEVICE = "EP1K10TC100-1";

    "in0"                          : INPUT_PIN  = 38     ;
    "in1"                          : INPUT_PIN  = 40     ;
    "out0"                         : OUTPUT_PIN = 58     ;
    "out1"                         : OUTPUT_PIN = 55     ;
    "out2"                         : OUTPUT_PIN = 56     ;
    "out3"                         : OUTPUT_PIN = 57     ;
    ":3"                           : LOCATION   = LC1_C5 ;
    ":4"                           : LOCATION   = LC7_C5 ;
    ":5"                           : LOCATION   = LC5_C5 ;
    ":6"                           : LOCATION   = LC3_C5 ;

END;

INTERNAL_INFO "logic_encoder"
BEGIN
	DEVICE = EP1K10TC100-1;
    OD2P38  : LORAX = "1:FB2|2:FH2R2,PA6R2C4->LC1_C5,->LC7_C5,->LC5_C5,->LC3_C5||";
    OD3P40  : LORAX = "1:FB3|2:FH3R2,PA5R2C4->LC1_C5,->LC7_C5,->LC5_C5,->LC3_C5||";
    LC1_C5  : LORAX = "1:MSW0R2C5,HHL20R2->OH8R2P58|";
    LC7_C5  : LORAX = "1:MSW6R2C4,HHL31R2->OH14R2P55|";
    LC5_C5  : LORAX = "1:MSW4R2C5,G77R2->OH12R2P56|";
    LC3_C5  : LORAX = "1:MSW2R2C4,HHL0R2->OH10R2P57|";
	LC1_C5  : LORAX2 = "X, X, OD2P38, OD3P40";
	LC7_C5  : LORAX2 = "X, X, OD2P38, OD3P40";
	LC5_C5  : LORAX2 = "X, X, OD2P38, OD3P40";
	LC3_C5  : LORAX2 = "X, X, OD2P38, OD3P40";
END;