📄 logic_7474.rpt
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Device-Specific Information: g:\khf-5 example\exa01\exa01\logic_7474.rpt
logic_7474
** CLOCK SIGNALS **
Type Fan-out Name
DFF 3 |7474:1|1Q
INPUT 1 cp
Device-Specific Information: g:\khf-5 example\exa01\exa01\logic_7474.rpt
logic_7474
** EQUATIONS **
cp : INPUT;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC3_C49;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC5_C49;
-- Node name is '|7474:1|:9' = '|7474:1|1Q'
-- Equation name is '_LC3_C49', type is buried
_LC3_C49 = DFFE(!_LC3_C49, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|7474:1|:10' = '|7474:1|2Q'
-- Equation name is '_LC5_C49', type is buried
_LC5_C49 = DFFE(!_LC5_C49, !_LC3_C49, VCC, VCC, VCC);
Project Information g:\khf-5 example\exa01\exa01\logic_7474.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:06
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 52,491K
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