📄 traffic_fsm.rpt
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| | | | | | | | +----------- LC24 rebn_ff5
| | | | | | | | | +--------- LC22 rebn_ff4
| | | | | | | | | | +------- LC21 rebn_ff3
| | | | | | | | | | | +----- LC20 rebn_ff2
| | | | | | | | | | | | +--- LC25 rebn_ff1
| | | | | | | | | | | | | +- LC23 rebn_ff0
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC28 -> - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|gcp2
LC29 -> - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node5
LC27 -> - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:118|addcore:adder|addcore:adder0|gcp2
LC19 -> - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:118|addcore:adder|addcore:adder0|result_node5
LC17 -> - - - - - - - * - - - - - - | * * | <-- st_transfer
LC24 -> - - - * - * - * * * * * * * | - * | <-- rebn_ff5
LC22 -> - - - * - * - * * * * * * * | - * | <-- rebn_ff4
LC21 -> - - - * - * - * * * * * * * | - * | <-- rebn_ff3
LC20 -> - - * * * * - * * * * * * * | - * | <-- rebn_ff2
LC25 -> - - * * * * - * * * * * * * | - * | <-- rebn_ff1
LC23 -> - - - * - * - * * * * * * * | - * | <-- rebn_ff0
Pin
43 -> - - - - - - - - - - - - - - | - - | <-- clk
5 -> - - - - - - - * * * * * * * | * * | <-- ena_scan
4 -> - - - - - - - * * * * * * * | * * | <-- reset
12 -> - - - - - - - * * * * * * * | - * | <-- st_butt
LC11 -> * * - - - - * - - - - - - - | * * | <-- red1
LC1 -> * * - - - - - - - - - - - - | * * | <-- state0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\traffic_fsm.rpt
traffic_fsm
** EQUATIONS **
clk : INPUT;
ena_scan : INPUT;
ena_1Hz : INPUT;
flash_1Hz : INPUT;
m : INPUT;
next_state : INPUT;
reset : INPUT;
st_butt : INPUT;
-- Node name is 'green0'
-- Equation name is 'green0', location is LC026, type is output.
green0 = LCELL( _EQ001 $ GND);
_EQ001 = red1 & !state0;
-- Node name is 'green1'
-- Equation name is 'green1', location is LC030, type is output.
green1 = LCELL( _EQ002 $ GND);
_EQ002 = !red1 & !state0;
-- Node name is ':41' = 'rebn_ff0'
-- Equation name is 'rebn_ff0', location is LC023, type is buried.
rebn_ff0 = TFFE(!_EQ003, GLOBAL( clk), VCC, !_EQ004, VCC);
_EQ003 = ena_scan & rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 &
!rebn_ff4 & !rebn_ff5
# !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 & !rebn_ff4 &
!rebn_ff5
# !ena_scan;
_EQ004 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is ':40' = 'rebn_ff1'
-- Equation name is 'rebn_ff1', location is LC025, type is buried.
rebn_ff1 = DFFE( _EQ005 $ VCC, GLOBAL( clk), VCC, !_EQ006, VCC);
_EQ005 = !rebn_ff1 & !rebn_ff2 & !rebn_ff3 & !rebn_ff4 & !rebn_ff5
# ena_scan & !rebn_ff0 & rebn_ff1
# rebn_ff0 & !rebn_ff1
# !ena_scan & !rebn_ff1;
_EQ006 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is ':39' = 'rebn_ff2'
-- Equation name is 'rebn_ff2', location is LC020, type is buried.
rebn_ff2 = TFFE( _EQ007, GLOBAL( clk), VCC, !_EQ008, VCC);
_EQ007 = ena_scan & !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & rebn_ff5
# ena_scan & !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & rebn_ff4
# ena_scan & !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & rebn_ff3
# ena_scan & !rebn_ff0 & !rebn_ff1 & rebn_ff2;
_EQ008 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is ':38' = 'rebn_ff3'
-- Equation name is 'rebn_ff3', location is LC021, type is buried.
rebn_ff3 = TFFE( _EQ009, GLOBAL( clk), VCC, !_EQ010, VCC);
_EQ009 = ena_scan & !_LC027 & !rebn_ff0 & rebn_ff1 & !rebn_ff2 &
!rebn_ff3 & !rebn_ff4 & !rebn_ff5
# ena_scan & !_LC028 & !rebn_ff0 & !rebn_ff3 & _X002
# ena_scan & !_LC028 & !rebn_ff0 & rebn_ff3;
_X002 = EXP(!rebn_ff2 & !rebn_ff4 & !rebn_ff5);
_EQ010 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is ':37' = 'rebn_ff4'
-- Equation name is 'rebn_ff4', location is LC022, type is buried.
rebn_ff4 = TFFE( _EQ011, GLOBAL( clk), VCC, !_EQ012, VCC);
_EQ011 = ena_scan & !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 &
!rebn_ff4 & _X003
# ena_scan & !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 &
rebn_ff4;
_X003 = EXP(!rebn_ff2 & !rebn_ff3 & !rebn_ff5);
_EQ012 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is ':36' = 'rebn_ff5'
-- Equation name is 'rebn_ff5', location is LC024, type is buried.
rebn_ff5 = DFFE( _EQ013 $ GND, GLOBAL( clk), VCC, !_EQ014, VCC);
_EQ013 = ena_scan & _LC019 & !rebn_ff0 & rebn_ff1 & !rebn_ff2 &
!rebn_ff3 & !rebn_ff4 & !rebn_ff5
# ena_scan & _LC029 & rebn_ff0 & rebn_ff1
# ena_scan & _LC029 & _X004
# !ena_scan & rebn_ff5;
_X004 = EXP(!rebn_ff2 & !rebn_ff3 & !rebn_ff4 & !rebn_ff5);
_EQ014 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is 'recount' = ':9'
-- Equation name is 'recount', type is output
recount = DFFE( _EQ015 $ VCC, GLOBAL( clk), VCC, !reset, VCC);
_EQ015 = ena_1Hz & m & !next_state
# !ena_1Hz & m & !recount
# !ena_scan & !m & !recount;
-- Node name is 'red0'
-- Equation name is 'red0', location is LC018, type is output.
red0 = LCELL( red1 $ VCC);
-- Node name is 'red1' = 'state1'
-- Equation name is 'red1', location is LC011, type is output.
red1 = DFFE( _EQ016 $ !_LC004, GLOBAL( clk), !reset, VCC, VCC);
_EQ016 = ena_1Hz & !_LC004 & m & next_state & red1 & state0
# ena_scan & !_LC004 & !m & red1 & state0 & st_transfer
# !_LC004 & m & !next_state & !red1;
-- Node name is 'sign_state0' = ':13'
-- Equation name is 'sign_state0', type is output
sign_state0 = DFFE( _EQ017 $ _EQ018, GLOBAL( clk), VCC, !reset, VCC);
_EQ017 = ena_1Hz & m & next_state & state0 & _X005 & _X006 & _X007 &
_X008
# ena_scan & !m & state0 & st_transfer & _X005 & _X006 & _X007 &
_X008
# m & !next_state & !sign_state0 & _X005 & _X006 & _X007 &
_X008;
_X005 = EXP(!m & !sign_state0 & !st_transfer);
_X006 = EXP(!ena_1Hz & m & !sign_state0);
_X007 = EXP(!ena_scan & !m & !sign_state0);
_X008 = EXP(!sign_state0 & state0);
_EQ018 = _X005 & _X006 & _X007 & _X008;
_X005 = EXP(!m & !sign_state0 & !st_transfer);
_X006 = EXP(!ena_1Hz & m & !sign_state0);
_X007 = EXP(!ena_scan & !m & !sign_state0);
_X008 = EXP(!sign_state0 & state0);
-- Node name is 'sign_state1' = ':11'
-- Equation name is 'sign_state1', type is output
sign_state1 = DFFE( _EQ019 $ _EQ020, GLOBAL( clk), !reset, VCC, VCC);
_EQ019 = ena_1Hz & !_LC008 & m & next_state & red1 & state0 & _X009 &
_X010
# ena_scan & !_LC008 & !m & red1 & state0 & st_transfer & _X009 &
_X010
# ena_1Hz & !_LC008 & m & next_state & !red1 & !state0 & _X009 &
_X010;
_X009 = EXP(!m & !sign_state1 & !st_transfer);
_X010 = EXP(!ena_scan & !m & !sign_state1);
_EQ020 = !_LC008 & _X009 & _X010;
_X009 = EXP(!m & !sign_state1 & !st_transfer);
_X010 = EXP(!ena_scan & !m & !sign_state1);
-- Node name is ':24' = 'state0'
-- Equation name is 'state0', location is LC001, type is buried.
state0 = DFFE( _EQ021 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ021 = ena_1Hz & m & next_state & !state0
# ena_scan & !m & !state0 & st_transfer
# m & state0 & _X011
# !m & state0 & _X012;
_X011 = EXP( ena_1Hz & next_state);
_X012 = EXP( ena_scan & st_transfer);
-- Node name is ':21' = 'st_transfer'
-- Equation name is 'st_transfer', location is LC017, type is buried.
st_transfer = DFFE( _EQ022 $ GND, GLOBAL( clk), !_EQ023, VCC, VCC);
_EQ022 = ena_scan & !rebn_ff0 & rebn_ff1 & !rebn_ff2 & !rebn_ff3 &
!rebn_ff4 & !rebn_ff5
# !ena_scan & st_transfer;
_EQ023 = _X001;
_X001 = EXP(!reset & !st_butt);
-- Node name is 'yellow0'
-- Equation name is 'yellow0', location is LC014, type is output.
yellow0 = LCELL( _EQ024 $ GND);
_EQ024 = flash_1Hz & red1 & state0;
-- Node name is 'yellow1'
-- Equation name is 'yellow1', location is LC013, type is output.
yellow1 = LCELL( _EQ025 $ GND);
_EQ025 = flash_1Hz & !red1 & state0;
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ026 $ rebn_ff2);
_EQ026 = rebn_ff1 & !rebn_ff2;
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( rebn_ff5 $ _EQ027);
_EQ027 = !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 & !rebn_ff4;
-- Node name is '|LPM_ADD_SUB:118|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ028 $ rebn_ff2);
_EQ028 = rebn_ff1 & !rebn_ff2;
-- Node name is '|LPM_ADD_SUB:118|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( rebn_ff5 $ _EQ029);
_EQ029 = !rebn_ff0 & !rebn_ff1 & !rebn_ff2 & !rebn_ff3 & !rebn_ff4;
-- Node name is '~1377~1'
-- Equation name is '~1377~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ030 $ GND);
_EQ030 = !ena_1Hz & m & !red1
# !m & !red1 & !st_transfer
# !ena_scan & !m & !red1
# !red1 & !state0;
-- Node name is '~1407~1'
-- Equation name is '~1407~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ031 $ GND);
_EQ031 = ena_scan & !m & !red1 & !state0 & st_transfer
# red1 & !sign_state1 & state0
# m & !next_state & !sign_state1
# !ena_1Hz & m & !sign_state1
# !red1 & !sign_state1 & !state0;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\working\vhdl312vh6\traffic_fsm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,726K
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