traffic_mux.rpt

包含若干个VHDL小例子

  41     17    B         FF   +  t        0      0   0    4    1    1    0  load4
  39     19    B         FF   +  t        0      0   0    3    1    1    0  load5
  33     24    B         FF   +  t        0      0   0    3    1    1    0  load6
  29     27    B         FF   +  t        0      0   0    3    1    1    0  load7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:             d:\working\vhdl312vh6\traffic_mux.rpt
traffic_mux

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC22 load0
        | +------------- LC23 load1
        | | +----------- LC21 load2
        | | | +--------- LC18 load3
        | | | | +------- LC17 load4
        | | | | | +----- LC19 load5
        | | | | | | +--- LC24 load6
        | | | | | | | +- LC27 load7
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * - - - - - - - | - * | <-- load0
LC23 -> - * - - - - - - | - * | <-- load1
LC21 -> - - * - - - - - | - * | <-- load2
LC18 -> - - - * - - - - | - * | <-- load3
LC17 -> - - - - * - - - | - * | <-- load4
LC19 -> - - - - - * - - | - * | <-- load5
LC24 -> - - - - - - * - | - * | <-- load6
LC27 -> - - - - - - - * | - * | <-- load7

Pin
43   -> - - - - - - - - | - - | <-- clk
4    -> * * * * * * * * | - * | <-- ena_scan
8    -> * * * * * * * * | - * | <-- recount
6    -> * * * * * * * * | - * | <-- reset
5    -> * - - - * - - - | - * | <-- sign_state0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:             d:\working\vhdl312vh6\traffic_mux.rpt
traffic_mux

** EQUATIONS **

clk      : INPUT;
ena_scan : INPUT;
recount  : INPUT;
reset    : INPUT;
sign_state0 : INPUT;

-- Node name is 'load0' = ':21' 
-- Equation name is 'load0', type is output 
 load0   = TFFE( _EQ001, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ001 =  ena_scan & !load0 &  recount &  sign_state0
         #  ena_scan &  load0 &  recount & !sign_state0;

-- Node name is 'load1' = ':19' 
-- Equation name is 'load1', type is output 
 load1   = TFFE( _EQ002, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ002 =  ena_scan &  load1 &  recount;

-- Node name is 'load2' = ':17' 
-- Equation name is 'load2', type is output 
 load2   = TFFE( _EQ003, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ003 =  ena_scan & !load2 &  recount;

-- Node name is 'load3' = ':15' 
-- Equation name is 'load3', type is output 
 load3   = TFFE( _EQ004, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ004 =  ena_scan &  load3 &  recount;

-- Node name is 'load4' = ':13' 
-- Equation name is 'load4', type is output 
 load4   = TFFE( _EQ005, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ005 =  ena_scan &  load4 &  recount &  sign_state0
         #  ena_scan & !load4 &  recount & !sign_state0;

-- Node name is 'load5' = ':11' 
-- Equation name is 'load5', type is output 
 load5   = TFFE( _EQ006, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ006 =  ena_scan &  load5 &  recount;

-- Node name is 'load6' = ':9' 
-- Equation name is 'load6', type is output 
 load6   = TFFE( _EQ007, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ007 =  ena_scan &  load6 &  recount;

-- Node name is 'load7' = ':7' 
-- Equation name is 'load7', type is output 
 load7   = TFFE( _EQ008, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ008 =  ena_scan &  load7 &  recount;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                      d:\working\vhdl312vh6\traffic_mux.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,889K