bcd_7seg.vhd

来自「包含若干个VHDL小例子」· VHDL 代码 · 共 26 行

--bcd_7seg.vhd bcd to 7 segment encoder
library ieee ;
use ieee.std_logic_1164.all;
entity bcd_7seg is
port(
  bcd_led : in std_logic_vector(3 downto 0);--input bcd
  ledseg : out std_logic_vector(6 downto 0));--output to 7 segment
end bcd_7seg;
architecture behavior of bcd_7seg is 
begin 
    with bcd_led select
    ledseg<="0111111" when "0000",--0
            "0000110" when "0001",--1
            "1011011" when "0010",--2
            "1001111" when "0011",--3
            "1100110" when "0100",--4
            "1101101" when "0101",--5
            "1111101" when "0110",--6
            "0100111" when "0111",--7
            "1111111" when "1000",--8
            "1101111" when "1001",--9
            "1000000" when "1110",--minus
            "0000000" when others;
end behavior;