📄 count_down.rpt
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!cnt_ff6 & !cnt_ff7);
_X009 = EXP(!cnt_ff0 & cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
-- Node name is 'seg73' = ':37'
-- Equation name is 'seg73', type is output
seg73 = DFFE( _EQ016 $ _EQ017, GLOBAL( clk), !reset, VCC, VCC);
_EQ016 = !cnt_ff0 & cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X010 & _X011 & _X012
# cnt_ff0 & cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X010 & _X011 & _X012
# !cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X010 & _X011 & _X012;
_X001 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X010 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X011 = EXP( cnt_ff0 & cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X012 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_EQ017 = _X001 & _X010 & _X011 & _X012;
_X001 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X010 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X011 = EXP( cnt_ff0 & cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X012 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
-- Node name is 'seg74' = ':35'
-- Equation name is 'seg74', type is output
seg74 = DFFE( _EQ018 $ _EQ019, GLOBAL( clk), !reset, VCC, VCC);
_EQ018 = cnt_ff0 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X013 & _X014 & _X015 & _X016 & _X017
# cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X013 & _X014 & _X015 & _X016 & _X017
# !cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X013 & _X014 & _X015 & _X016 & _X017;
_X013 = EXP(!cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X014 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X015 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X016 = EXP( cnt_ff0 & cnt_ff1 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X017 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_EQ019 = _X013 & _X014 & _X015 & _X016 & _X017;
_X013 = EXP(!cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X014 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X015 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X016 = EXP( cnt_ff0 & cnt_ff1 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
_X017 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7);
-- Node name is 'seg75' = ':33'
-- Equation name is 'seg75', type is output
seg75 = DFFE( _EQ020 $ _EQ021, GLOBAL( clk), !reset, VCC, VCC);
_EQ020 = cnt_ff0 & cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X010 & _X018 & _X019 & _X020
# cnt_ff0 & cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X010 & _X018 & _X019 & _X020
# cnt_ff1 & cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7 & _X010 & _X018 & _X019 & _X020;
_X010 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X018 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X019 = EXP(!cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X020 = EXP( cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_EQ021 = _X010 & _X018 & _X019 & _X020;
_X010 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X018 = EXP( cnt_ff0 & cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X019 = EXP(!cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
_X020 = EXP( cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7);
-- Node name is 'seg76' = ':31'
-- Equation name is 'seg76', type is output
seg76 = DFFE( _EQ022 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ022 = cnt_ff1 & !cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7 & _X021
# cnt_ff2 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7 & _X022
# !cnt_ff0 & !cnt_ff2 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff1 & cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
_X021 = EXP( cnt_ff2 & !cnt_ff4);
_X022 = EXP( cnt_ff0 & cnt_ff1 & !cnt_ff3);
-- Node name is 'seg77'
-- Equation name is 'seg77', location is LC051, type is output.
seg77 = LCELL( GND $ GND);
-- Node name is 'seg78' = ':27'
-- Equation name is 'seg78', type is output
seg78 = DFFE( _EQ023 $ VCC, GLOBAL( clk), !reset, VCC, VCC);
_EQ023 = cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# cnt_ff1 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg79' = ':25'
-- Equation name is 'seg79', type is output
seg79 = DFFE( GND $ VCC, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is 'seg710' = ':23'
-- Equation name is 'seg710', type is output
seg710 = DFFE( _EQ024 $ VCC, GLOBAL( clk), !reset, VCC, VCC);
_EQ024 = cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7
# cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff1 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg711' = ':21'
-- Equation name is 'seg711', type is output
seg711 = DFFE( _EQ025 $ VCC, GLOBAL( clk), !reset, VCC, VCC);
_EQ025 = cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# cnt_ff1 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg712' = ':19'
-- Equation name is 'seg712', type is output
seg712 = DFFE( _EQ026 $ VCC, GLOBAL( clk), !reset, VCC, VCC);
_EQ026 = cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# cnt_ff1 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg713' = ':17'
-- Equation name is 'seg713', type is output
seg713 = DFFE( _EQ027 $ VCC, GLOBAL( clk), !reset, VCC, VCC);
_EQ027 = !cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# cnt_ff1 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff2 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg714' = ':15'
-- Equation name is 'seg714', type is output
seg714 = DFFE( _EQ028 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ028 = !cnt_ff1 & cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 &
!cnt_ff7
# cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7
# !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 & !cnt_ff6 & !cnt_ff7;
-- Node name is 'seg715'
-- Equation name is 'seg715', location is LC053, type is output.
seg715 = LCELL( GND $ GND);
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC064', type is buried
_LC064 = LCELL( load1 $ !load0);
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried
_LC063 = LCELL( load2 $ _EQ029);
_EQ029 = !load0 & !load1;
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried
_LC062 = LCELL( load3 $ _EQ030);
_EQ030 = !load0 & !load1 & !load2;
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( load4 $ _EQ031);
_EQ031 = !load0 & !load1 & !load2 & !load3;
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried
_LC060 = LCELL( load5 $ _EQ032);
_EQ032 = !load0 & !load1 & !load2 & !load3 & !load4;
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC058', type is buried
_LC058 = LCELL( load6 $ _EQ033);
_EQ033 = !load0 & !load1 & !load2 & !load3 & !load4 & !load5;
-- Node name is '|LPM_ADD_SUB:695|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( load7 $ _EQ034);
_EQ034 = !load0 & !load1 & !load2 & !load3 & !load4 & !load5 & !load6;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( cnt_ff1 $ !cnt_ff0);
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( cnt_ff2 $ _EQ035);
_EQ035 = !cnt_ff0 & !cnt_ff1;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC006', type is buried
_LC006 = LCELL( cnt_ff3 $ _EQ036);
_EQ036 = !cnt_ff0 & !cnt_ff1 & !cnt_ff2;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( cnt_ff4 $ _EQ037);
_EQ037 = !cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried
_LC044 = LCELL( cnt_ff5 $ _EQ038);
_EQ038 = !cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried
_LC047 = LCELL( cnt_ff6 $ _EQ039);
_EQ039 = !cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5;
-- Node name is '|LPM_ADD_SUB:736|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC048', type is buried
_LC048 = LCELL( cnt_ff7 $ _EQ040);
_EQ040 = !cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, C
Project Information d:\working\vhdl312vh6\count_down.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,815K
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