📄 count_down.rpt
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Logic cells placed in LAB 'A'
+------- LC6 |LPM_ADD_SUB:736|addcore:adder|result_node3
| +----- LC4 seg73
| | +--- LC1 seg75
| | | +- LC3 seg76
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D | Logic cells that feed LAB 'A':
Pin
43 -> - - - - | - - - - | <-- clk
17 -> - * * * | * * * * | <-- reset
LC38 -> - * * * | * * * - | <-- cnt_ff7
LC45 -> - * * * | * * * - | <-- cnt_ff6
LC43 -> - * * * | * * * - | <-- cnt_ff5
LC42 -> - * * * | * * * - | <-- cnt_ff4
LC34 -> * * * * | * * * - | <-- cnt_ff3
LC39 -> * * * * | * * * - | <-- cnt_ff2
LC49 -> * * * * | * * * * | <-- cnt_ff1
LC50 -> * * * * | * * * * | <-- cnt_ff0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------- LC31 |LPM_ADD_SUB:736|addcore:adder|result_node2
| +--------- LC32 |LPM_ADD_SUB:736|addcore:adder|result_node4
| | +------- LC17 next_state
| | | +----- LC19 seg71
| | | | +--- LC20 seg72
| | | | | +- LC30 seg74
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'B'
LC | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
43 -> - - - - - - | - - - - | <-- clk
17 -> - - - * * * | * * * * | <-- reset
LC38 -> - - * * * * | * * * - | <-- cnt_ff7
LC45 -> - - * * * * | * * * - | <-- cnt_ff6
LC43 -> - - * * * * | * * * - | <-- cnt_ff5
LC42 -> - * * * * * | * * * - | <-- cnt_ff4
LC34 -> - * * * * * | * * * - | <-- cnt_ff3
LC39 -> * * * * * * | * * * - | <-- cnt_ff2
LC49 -> * * * * * * | * * * * | <-- cnt_ff1
LC50 -> * * * * * * | * * * * | <-- cnt_ff0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC44 |LPM_ADD_SUB:736|addcore:adder|result_node5
| +----------------------------- LC47 |LPM_ADD_SUB:736|addcore:adder|result_node6
| | +--------------------------- LC48 |LPM_ADD_SUB:736|addcore:adder|result_node7
| | | +------------------------- LC37 seg70
| | | | +----------------------- LC40 seg78
| | | | | +--------------------- LC41 seg710
| | | | | | +------------------- LC46 seg711
| | | | | | | +----------------- LC33 seg712
| | | | | | | | +--------------- LC35 seg713
| | | | | | | | | +------------- LC36 seg714
| | | | | | | | | | +----------- LC38 cnt_ff7
| | | | | | | | | | | +--------- LC45 cnt_ff6
| | | | | | | | | | | | +------- LC43 cnt_ff5
| | | | | | | | | | | | | +----- LC42 cnt_ff4
| | | | | | | | | | | | | | +--- LC34 cnt_ff3
| | | | | | | | | | | | | | | +- LC39 cnt_ff2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC44 -> - - - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node5
LC47 -> - - - - - - - - - - - * - - - - | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node6
LC48 -> - - - - - - - - - - * - - - - - | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node7
LC38 -> - - * * * * * * * * * - - - - - | * * * - | <-- cnt_ff7
LC45 -> - * * * * * * * * * - * - - - - | * * * - | <-- cnt_ff6
LC43 -> * * * * * * * * * * - - * - - - | * * * - | <-- cnt_ff5
LC42 -> * * * * * * * * * * - - - * - - | * * * - | <-- cnt_ff4
LC34 -> * * * * * * * * * * - - - - * - | * * * - | <-- cnt_ff3
LC39 -> * * * * * * * * * * - - - - - * | * * * - | <-- cnt_ff2
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
39 -> - - - - - - - - - - * * * * * * | - - * * | <-- ena_1Hz
16 -> - - - - - - - - - - * * * * * * | - - * * | <-- recount
17 -> - - - * * * * * * * * * * * * * | * * * * | <-- reset
LC63 -> - - - - - - - - - - - - - - - * | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node2
LC62 -> - - - - - - - - - - - - - - * - | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node3
LC61 -> - - - - - - - - - - - - - * - - | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node4
LC60 -> - - - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node5
LC58 -> - - - - - - - - - - - * - - - - | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node6
LC56 -> - - - - - - - - - - * - - - - - | - - * - | <-- |LPM_ADD_SUB:695|addcore:adder|result_node7
LC31 -> - - - - - - - - - - - - - - - * | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node2
LC6 -> - - - - - - - - - - - - - - * - | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node3
LC32 -> - - - - - - - - - - - - - * - - | - - * - | <-- |LPM_ADD_SUB:736|addcore:adder|result_node4
LC49 -> * * * * * * * * * * - - - - - - | * * * * | <-- cnt_ff1
LC50 -> * * * * - - - - - - - - - - - - | * * * * | <-- cnt_ff0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------- LC64 |LPM_ADD_SUB:695|addcore:adder|result_node1
| +----------------------- LC63 |LPM_ADD_SUB:695|addcore:adder|result_node2
| | +--------------------- LC62 |LPM_ADD_SUB:695|addcore:adder|result_node3
| | | +------------------- LC61 |LPM_ADD_SUB:695|addcore:adder|result_node4
| | | | +----------------- LC60 |LPM_ADD_SUB:695|addcore:adder|result_node5
| | | | | +--------------- LC58 |LPM_ADD_SUB:695|addcore:adder|result_node6
| | | | | | +------------- LC56 |LPM_ADD_SUB:695|addcore:adder|result_node7
| | | | | | | +----------- LC55 |LPM_ADD_SUB:736|addcore:adder|result_node1
| | | | | | | | +--------- LC51 seg77
| | | | | | | | | +------- LC52 seg79
| | | | | | | | | | +----- LC53 seg715
| | | | | | | | | | | +--- LC49 cnt_ff1
| | | | | | | | | | | | +- LC50 cnt_ff0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC64 -> - - - - - - - - - - - * - | - - - * | <-- |LPM_ADD_SUB:695|addcore:adder|result_node1
LC55 -> - - - - - - - - - - - * - | - - - * | <-- |LPM_ADD_SUB:736|addcore:adder|result_node1
LC49 -> - - - - - - - * - - - * - | * * * * | <-- cnt_ff1
LC50 -> - - - - - - - * - - - - * | * * * * | <-- cnt_ff0
Pin
43 -> - - - - - - - - - - - - - | - - - - | <-- clk
39 -> - - - - - - - - - - - * * | - - * * | <-- ena_1Hz
41 -> * * * * * * * - - - - - * | - - - * | <-- load0
18 -> * * * * * * * - - - - - - | - - - * | <-- load1
40 -> - * * * * * * - - - - - - | - - - * | <-- load2
4 -> - - * * * * * - - - - - - | - - - * | <-- load3
33 -> - - - * * * * - - - - - - | - - - * | <-- load4
5 -> - - - - * * * - - - - - - | - - - * | <-- load5
6 -> - - - - - * * - - - - - - | - - - * | <-- load6
8 -> - - - - - - * - - - - - - | - - - * | <-- load7
16 -> - - - - - - - - - - - * * | - - * * | <-- recount
17 -> - - - - - - - - - * - * * | * * * * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** EQUATIONS **
clk : INPUT;
ena_1Hz : INPUT;
load0 : INPUT;
load1 : INPUT;
load2 : INPUT;
load3 : INPUT;
load4 : INPUT;
load5 : INPUT;
load6 : INPUT;
load7 : INPUT;
recount : INPUT;
reset : INPUT;
-- Node name is ':53' = 'cnt_ff0'
-- Equation name is 'cnt_ff0', location is LC050, type is buried.
cnt_ff0 = DFFE( _EQ001 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = ena_1Hz & !load0 & recount
# !cnt_ff0 & ena_1Hz & !recount
# cnt_ff0 & !ena_1Hz;
-- Node name is ':52' = 'cnt_ff1'
-- Equation name is 'cnt_ff1', location is LC049, type is buried.
cnt_ff1 = DFFE( _EQ002 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = ena_1Hz & _LC064 & recount
# ena_1Hz & _LC055 & !recount
# cnt_ff1 & !ena_1Hz;
-- Node name is ':51' = 'cnt_ff2'
-- Equation name is 'cnt_ff2', location is LC039, type is buried.
cnt_ff2 = DFFE( _EQ003 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = ena_1Hz & _LC063 & recount
# ena_1Hz & _LC031 & !recount
# cnt_ff2 & !ena_1Hz;
-- Node name is ':50' = 'cnt_ff3'
-- Equation name is 'cnt_ff3', location is LC034, type is buried.
cnt_ff3 = DFFE( _EQ004 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = ena_1Hz & _LC062 & recount
# ena_1Hz & _LC006 & !recount
# cnt_ff3 & !ena_1Hz;
-- Node name is ':49' = 'cnt_ff4'
-- Equation name is 'cnt_ff4', location is LC042, type is buried.
cnt_ff4 = DFFE( _EQ005 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = ena_1Hz & _LC061 & recount
# ena_1Hz & _LC032 & !recount
# cnt_ff4 & !ena_1Hz;
-- Node name is ':48' = 'cnt_ff5'
-- Equation name is 'cnt_ff5', location is LC043, type is buried.
cnt_ff5 = DFFE( _EQ006 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = ena_1Hz & _LC060 & recount
# ena_1Hz & _LC044 & !recount
# cnt_ff5 & !ena_1Hz;
-- Node name is ':47' = 'cnt_ff6'
-- Equation name is 'cnt_ff6', location is LC045, type is buried.
cnt_ff6 = DFFE( _EQ007 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = ena_1Hz & _LC058 & recount
# ena_1Hz & _LC047 & !recount
# cnt_ff6 & !ena_1Hz;
-- Node name is ':46' = 'cnt_ff7'
-- Equation name is 'cnt_ff7', location is LC038, type is buried.
cnt_ff7 = DFFE( _EQ008 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ008 = ena_1Hz & _LC056 & recount
# ena_1Hz & _LC048 & !recount
# cnt_ff7 & !ena_1Hz;
-- Node name is 'next_state'
-- Equation name is 'next_state', location is LC017, type is output.
next_state = LCELL( _EQ009 $ GND);
_EQ009 = cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7;
-- Node name is 'seg70' = ':43'
-- Equation name is 'seg70', type is output
seg70 = DFFE( _EQ010 $ _EQ011, GLOBAL( clk), !reset, VCC, VCC);
_EQ010 = cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X002 & _X003
# !cnt_ff0 & cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X002 & _X003
# cnt_ff0 & cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X001 & _X002 & _X003;
_X001 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X002 = EXP(!cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X003 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_EQ011 = _X001 & _X002 & _X003;
_X001 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X002 = EXP(!cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X003 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
-- Node name is 'seg71' = ':41'
-- Equation name is 'seg71', type is output
seg71 = DFFE( _EQ012 $ _EQ013, GLOBAL( clk), !reset, VCC, VCC);
_EQ012 = cnt_ff0 & cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X004 & _X005 & _X006
# cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X004 & _X005 & _X006
# !cnt_ff0 & cnt_ff1 & !cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X004 & _X005 & _X006;
_X004 = EXP(!cnt_ff0 & cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X005 = EXP( cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X006 = EXP(!cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_EQ013 = _X004 & _X005 & _X006;
_X004 = EXP(!cnt_ff0 & cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X005 = EXP( cnt_ff0 & !cnt_ff1 & cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X006 = EXP(!cnt_ff0 & !cnt_ff1 & !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
-- Node name is 'seg72' = ':39'
-- Equation name is 'seg72', type is output
seg72 = DFFE( _EQ014 $ _EQ015, GLOBAL( clk), !reset, VCC, VCC);
_EQ014 = cnt_ff0 & !cnt_ff1 & cnt_ff2 & cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X007 & _X008 & _X009
# !cnt_ff0 & cnt_ff1 & cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X007 & _X008 & _X009
# cnt_ff0 & cnt_ff1 & !cnt_ff2 & !cnt_ff3 & cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7 & _X007 & _X008 & _X009;
_X007 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X008 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X009 = EXP(!cnt_ff0 & cnt_ff1 & !cnt_ff2 & !cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_EQ015 = _X007 & _X008 & _X009;
_X007 = EXP(!cnt_ff0 & !cnt_ff1 & cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
!cnt_ff6 & !cnt_ff7);
_X008 = EXP( cnt_ff0 & !cnt_ff1 & !cnt_ff2 & cnt_ff3 & !cnt_ff4 & !cnt_ff5 &
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