📄 count_down.rpt
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Project Information d:\working\vhdl312vh6\count_down.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/25/2008 22:42:53
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
COUNT_DOWN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
count_down
EPM7064SLC44-5 12 17 0 39 23 60 %
User Pins: 12 17 0
Project Information d:\working\vhdl312vh6\count_down.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':13' stuck at GND
Warning: Flipflop ':29' stuck at GND
Warning: Primitive 'seg715' is stuck at GND
Warning: Primitive 'seg77' is stuck at GND
Project Information d:\working\vhdl312vh6\count_down.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\working\vhdl312vh6\count_down.rpt
** FILE HIERARCHY **
|lpm_add_sub:695|
|lpm_add_sub:695|addcore:adder|
|lpm_add_sub:695|altshift:result_ext_latency_ffs|
|lpm_add_sub:695|altshift:carry_ext_latency_ffs|
|lpm_add_sub:695|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:736|
|lpm_add_sub:736|addcore:adder|
|lpm_add_sub:736|altshift:result_ext_latency_ffs|
|lpm_add_sub:736|altshift:carry_ext_latency_ffs|
|lpm_add_sub:736|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
***** Logic for device 'count_down' compiled without errors.
Device: EPM7064SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** ERROR SUMMARY **
Info: Chip 'count_down' in device 'EPM7064SLC44-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
l l l l l
o o o o o
a a a V G G G c G a a
d d d C N N N l N d d
6 5 3 C D D D k D 0 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | ena_1Hz
load7 | 8 38 | #TDO
seg73 | 9 37 | seg715
GND | 10 36 | seg79
seg76 | 11 35 | VCC
seg75 | 12 EPM7064SLC44-5 34 | seg77
#TMS | 13 33 | load4
seg74 | 14 32 | #TCK
VCC | 15 31 | seg711
recount | 16 30 | GND
reset | 17 29 | seg710
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
l s s n G V s s s s s
o e e e N C e e e e e
a g g x D C g g g g g
d 7 7 t 7 7 7 7 7
1 2 1 _ 1 1 1 0 8
s 2 3 4
t
a
t
e
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 4/16( 25%) 8/ 8(100%) 12/16( 75%) 9/36( 25%)
B: LC17 - LC32 6/16( 37%) 8/ 8(100%) 14/16( 87%) 9/36( 25%)
C: LC33 - LC48 16/16(100%) 8/ 8(100%) 5/16( 31%) 23/36( 63%)
D: LC49 - LC64 13/16( 81%) 8/ 8(100%) 0/16( 0%) 15/36( 41%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 39/64 ( 60%)
Total shareable expanders used: 23/64 ( 35%)
Total Turbo logic cells used: 39/64 ( 60%)
Total shareable expanders not available (n/a): 8/64 ( 12%)
Average fan-in: 6.64
Total fan-in: 259
Total input pins required: 12
Total fast input logic cells required: 0
Total output pins required: 17
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 39
Total flipflops required: 22
Total product terms required: 148
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 22
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
39 (57) (D) INPUT 0 0 0 0 0 0 8 ena_1Hz
41 (64) (D) INPUT 0 0 0 0 0 0 8 load0
18 (21) (B) INPUT 0 0 0 0 0 0 7 load1
40 (62) (D) INPUT 0 0 0 0 0 0 6 load2
4 (16) (A) INPUT 0 0 0 0 0 0 5 load3
33 (49) (D) INPUT 0 0 0 0 0 0 4 load4
5 (14) (A) INPUT 0 0 0 0 0 0 3 load5
6 (11) (A) INPUT 0 0 0 0 0 0 2 load6
8 (5) (A) INPUT 0 0 0 0 0 0 1 load7
16 (25) (B) INPUT 0 0 0 0 0 0 8 recount
17 (24) (B) INPUT 0 0 0 0 0 14 8 reset
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
21 17 B OUTPUT t 0 0 0 0 8 0 0 next_state
27 37 C FF + t 4 1 1 1 8 0 0 seg70
20 19 B FF + t 4 0 1 1 8 0 0 seg71
19 20 B FF + t 4 0 1 1 8 0 0 seg72
9 4 A FF + t 5 2 1 1 8 0 0 seg73
14 30 B FF + t 6 0 1 1 8 0 0 seg74
12 1 A FF + t 5 1 1 1 8 0 0 seg75
11 3 A FF + t 3 0 1 1 8 0 0 seg76
34 51 D OUTPUT t 0 0 0 0 0 0 0 seg77
28 40 C FF + t 0 0 0 1 7 0 0 seg78
36 52 D FF + t 0 0 0 1 0 0 0 seg79
29 41 C FF + t 0 0 0 1 7 0 0 seg710
31 46 C FF + t 0 0 0 1 7 0 0 seg711
24 33 C FF + t 0 0 0 1 7 0 0 seg712
25 35 C FF + t 1 0 1 1 7 0 0 seg713
26 36 C FF + t 0 0 0 1 7 0 0 seg714
37 53 D OUTPUT t 0 0 0 0 0 0 0 seg715
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(41) 64 D SOFT t 0 0 0 2 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node1
- 63 D SOFT t 0 0 0 3 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node2
(40) 62 D SOFT t 0 0 0 4 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node3
- 61 D SOFT t 0 0 0 5 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node4
- 60 D SOFT t 0 0 0 6 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node5
- 58 D SOFT t 0 0 0 7 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node6
(38) 56 D SOFT t 0 0 0 8 0 0 1 |LPM_ADD_SUB:695|addcore:adder|result_node7
- 55 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node1
- 31 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node2
- 6 A SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node3
(13) 32 B SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node4
- 44 C SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node5
- 47 C SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node6
(32) 48 C SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:736|addcore:adder|result_node7
- 38 C DFFE + t 0 0 0 3 3 14 2 cnt_ff7 (:46)
- 45 C DFFE + t 0 0 0 3 3 14 3 cnt_ff6 (:47)
- 43 C DFFE + t 0 0 0 3 3 14 4 cnt_ff5 (:48)
- 42 C DFFE + t 0 0 0 3 3 14 5 cnt_ff4 (:49)
- 34 C DFFE + t 0 0 0 3 3 14 6 cnt_ff3 (:50)
- 39 C DFFE + t 0 0 0 3 3 14 7 cnt_ff2 (:51)
(33) 49 D DFFE + t 0 0 0 3 3 14 8 cnt_ff1 (:52)
- 50 D DFFE + t 0 0 0 4 1 8 8 cnt_ff0 (:53)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\working\vhdl312vh6\count_down.rpt
count_down
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
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