📄 clk_gen.rpt
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clk_gen
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC18 ena_scan
| +----------------------------- LC24 ena_1Hz
| | +--------------------------- LC17 flash_1Hz
| | | +------------------------- LC20 |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node1
| | | | +----------------------- LC21 |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node5
| | | | | +--------------------- LC22 |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node6
| | | | | | +------------------- LC19 clk_scan_ff1
| | | | | | | +----------------- LC23 clk_scan_ff0
| | | | | | | | +--------------- LC32 ena_two
| | | | | | | | | +------------- LC31 clk_2Hz_ff6
| | | | | | | | | | +----------- LC30 clk_2Hz_ff5
| | | | | | | | | | | +--------- LC29 clk_2Hz_ff4
| | | | | | | | | | | | +------- LC28 clk_2Hz_ff3
| | | | | | | | | | | | | +----- LC27 clk_2Hz_ff2
| | | | | | | | | | | | | | +--- LC26 clk_2Hz_ff1
| | | | | | | | | | | | | | | +- LC25 clk_2Hz_ff0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> - * * - - - - - * * * * * * * * | - * | <-- ena_scan
LC17 -> - * * - - - - - - - - - - - - - | - * | <-- flash_1Hz
LC20 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node1
LC21 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node5
LC22 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node6
LC19 -> * - - - - - * - - - - - - - - - | - * | <-- clk_scan_ff1
LC23 -> * - - - - - * * - - - - - - - - | - * | <-- clk_scan_ff0
LC32 -> - * - - - - - - * - - - - - - - | - * | <-- ena_two
LC31 -> - - * - - * - - * * * * * * * * | - * | <-- clk_2Hz_ff6
LC30 -> - - * - * * - - * * * * * * * * | - * | <-- clk_2Hz_ff5
LC29 -> - - * - * * - - * * * * * * * * | - * | <-- clk_2Hz_ff4
LC28 -> - - * - * * - - * * * * * * * * | - * | <-- clk_2Hz_ff3
LC27 -> - - * - * * - - * * * * * * * * | - * | <-- clk_2Hz_ff2
LC26 -> - - - * * * - - - - - * * * * - | - * | <-- clk_2Hz_ff1
LC25 -> - - - * * * - - - - - * * * - * | - * | <-- clk_2Hz_ff0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> * - * - - - * * * * * * * * * * | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\working\vhdl312vh6\clk_gen.rpt
clk_gen
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':7' = 'clk_scan_ff0'
-- Equation name is 'clk_scan_ff0', location is LC023, type is buried.
clk_scan_ff0 = TFFE( VCC, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':6' = 'clk_scan_ff1'
-- Equation name is 'clk_scan_ff1', location is LC019, type is buried.
clk_scan_ff1 = TFFE( clk_scan_ff0, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':17' = 'clk_2Hz_ff0'
-- Equation name is 'clk_2Hz_ff0', location is LC025, type is buried.
clk_2Hz_ff0 = TFFE(!_EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = !clk_2Hz_ff0 & clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 &
clk_2Hz_ff5 & clk_2Hz_ff6 & ena_scan
# !ena_scan;
-- Node name is ':16' = 'clk_2Hz_ff1'
-- Equation name is 'clk_2Hz_ff1', location is LC026, type is buried.
clk_2Hz_ff1 = DFFE( _EQ002 $ _LC020, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan & _LC020
# clk_2Hz_ff1 & !ena_scan & !_LC020
# !clk_2Hz_ff1 & !ena_scan & _LC020;
-- Node name is ':15' = 'clk_2Hz_ff2'
-- Equation name is 'clk_2Hz_ff2', location is LC027, type is buried.
clk_2Hz_ff2 = TFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan
# clk_2Hz_ff0 & clk_2Hz_ff1 & ena_scan;
-- Node name is ':14' = 'clk_2Hz_ff3'
-- Equation name is 'clk_2Hz_ff3', location is LC028, type is buried.
clk_2Hz_ff3 = TFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan
# clk_2Hz_ff0 & clk_2Hz_ff1 & clk_2Hz_ff2 & ena_scan;
-- Node name is ':13' = 'clk_2Hz_ff4'
-- Equation name is 'clk_2Hz_ff4', location is LC029, type is buried.
clk_2Hz_ff4 = TFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan
# clk_2Hz_ff0 & clk_2Hz_ff1 & clk_2Hz_ff2 & clk_2Hz_ff3 &
ena_scan;
-- Node name is ':12' = 'clk_2Hz_ff5'
-- Equation name is 'clk_2Hz_ff5', location is LC030, type is buried.
clk_2Hz_ff5 = DFFE( _EQ006 $ _LC021, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan & _LC021
# clk_2Hz_ff5 & !ena_scan & !_LC021
# !clk_2Hz_ff5 & !ena_scan & _LC021;
-- Node name is ':11' = 'clk_2Hz_ff6'
-- Equation name is 'clk_2Hz_ff6', location is LC031, type is buried.
clk_2Hz_ff6 = DFFE( _EQ007 $ _LC022, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan & _LC022
# clk_2Hz_ff6 & !ena_scan & !_LC022
# !clk_2Hz_ff6 & !ena_scan & _LC022;
-- Node name is 'ena_scan' = 'ena_s'
-- Equation name is 'ena_scan', location is LC018, type is output.
ena_scan = DFFE( _EQ008 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ008 = clk_scan_ff0 & clk_scan_ff1;
-- Node name is ':10' = 'ena_two'
-- Equation name is 'ena_two', location is LC032, type is buried.
ena_two = DFFE( _EQ009 $ GND, GLOBAL( clk), !reset, VCC, VCC);
_EQ009 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan
# !ena_scan & ena_two;
-- Node name is 'ena_1Hz'
-- Equation name is 'ena_1Hz', location is LC024, type is output.
ena_1Hz = LCELL( _EQ010 $ GND);
_EQ010 = ena_scan & ena_two & flash_1Hz;
-- Node name is 'flash_1Hz' = 'ena_one'
-- Equation name is 'flash_1Hz', location is LC017, type is output.
flash_1Hz = TFFE( _EQ011, GLOBAL( clk), !reset, VCC, VCC);
_EQ011 = clk_2Hz_ff2 & clk_2Hz_ff3 & clk_2Hz_ff4 & clk_2Hz_ff5 &
clk_2Hz_ff6 & ena_scan;
-- Node name is '|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( clk_2Hz_ff1 $ clk_2Hz_ff0);
-- Node name is '|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( clk_2Hz_ff5 $ _EQ012);
_EQ012 = clk_2Hz_ff0 & clk_2Hz_ff1 & clk_2Hz_ff2 & clk_2Hz_ff3 &
clk_2Hz_ff4;
-- Node name is '|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( clk_2Hz_ff6 $ _EQ013);
_EQ013 = clk_2Hz_ff0 & clk_2Hz_ff1 & clk_2Hz_ff2 & clk_2Hz_ff3 &
clk_2Hz_ff4 & clk_2Hz_ff5;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\working\vhdl312vh6\clk_gen.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,783K
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