rs.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY rsff IS
    PORT(s :IN BIT;
           r :IN BIT;
           q :OUT BIT;
           qb :OUT BIT);
END rsff;
ARCHITECTURE rtl OF rsff IS
BEGIN
     PROCESS(s，r)
VARIABLE  last_state :BIT;
BEGIN
   ASSERT(NOT(s ='1' AND r ='1'))
   REPORT "Both s and r equal to '1'."
   SEVERITY  ERROR;
        IF(s ='0' AND r ='0')THEN
             last_state :=  last_state;
        ELSIF(s ='0'AND r ='1')THEN
             last_state := 0;
         ELSE
         last_state := 1;
         END IF;
            q <= last_state;
            qb <= not(last_state);
END PROCESS;
END rtl;