jk.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY jkdff IS
PORT(j, k : IN STD_LOGIC;
Clk : IN STD_LOGIC;
q, qb : OUT STD_LOGIC);
END jkdff;
ARCHITECTURE a OF jkdff IS
SIGNAL qtmp,qbtmp:STD_LOGIC;
BEGIN
PROCESS(clk,j,k)
BEGIN
IF clk='1' AND clk'event THEN
IF j='0' AND k='0' THEN NULL;
ELSIF j='0' AND k='1' THEN
qtmp<='0';
qbtmp<='1';
ELSIF j='1' AND k='0' THEN
qtmp<='1';
qbtmp<='0';
ELSE qtmp<=NOT qtmp;
qbtmp<=NOT qbtmp;
END IF;
END IF;
q<=qtmp;
qb<=qbtmp;
END PROCESS;
END a;