计数器.txt

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY adder IS
PORT(cr,ld,clk,a0,a1,a2,a3:IN STD_LOGIC;
                   q:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0); )
END adder;

ARCHITECTURE rt3 OF adder IS
SIGNAL indata:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
   PROCESS(clk)
   VARIABLE q10:INTEGER:=0; 
   BEGIN
     IF(cr='1') THEN
         IF(clk'EVENT AND clk='1')THEN
               IF(q=15) THEN
                  q:=0;

         ELSE
               q:=q+1;
              END IF;
       END IF;
  
       IF(cr='0')
              q:=0
   END IF; 
   indata<=CONV_STD_LOGIC_VECTOR(q10,4);
   q<=TO_STDULOGICVECTOR(indata);
   END PROCESS;
END ARCHITECTURE rt3;