d.txt

这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了……

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ddf1 IS

PORT
(
D,clk: IN STD_LOGIC;
Q: out STD_LOGIC
);

END ddf1;

ARCHITECTURE a1 OF ddf1 IS
BEGIN
signal sig_save: STD_LOGIC;

process(clk)
begin
if clk'event and clk='1' then
sig_save<=D;
end if;
Q<=sig_save;
end process;

END a1;