testctl.v

来自「用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）」· Verilog 代码 · 共 28 行

module testctl(clk,rst,tsten,clr_cnt,load);
	input	clk, rst;
	output	tsten, clr_cnt, load;
	reg		tsten,load,clr_cnt;
	
	
	initial		tsten = 1'b0;
	initial 	load  = 1'b1;
	initial		clr_cnt = 1'b0;

	
	always @(posedge clk)
		if(!rst)
			begin 
			tsten = ~ tsten;
			load  = ~ load;
			end
			
			
	always @(clk)
			begin
			if(!clk&&load)
				clr_cnt = 1'b1;
			else
				clr_cnt = 1'b0;
			end			
endmodule