testctl.hif

来自「用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）」· HIF 代码 · 共 177 行

Version 8.0 Build 215 05/29/2008 SJ Full Version
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OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
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VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
fequency
# storage
db|testctl.(0).cnf
db|testctl.(0).cnf
# case_insensitive
# source_file
fequency.bdf
a4af5dc8b723fa5a6c21465fa421c3b
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# macro_sequence

# end
# entity
testctl
# storage
db|testctl.(2).cnf
db|testctl.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
testctl.v
dbd8fc3bc393838a6bf20b2dda34583
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
reg32b
# storage
db|testctl.(3).cnf
db|testctl.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
reg32b.v
1a3272fe72a98c570b3fbbc6c8891
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
cout4
# storage
db|testctl.(1).cnf
db|testctl.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cout4.v
44b6182e42dfcebe574b2621f9284db
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
second
# storage
db|testctl.(4).cnf
db|testctl.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
second.v
b9a47d218afc688389492672c135ba42
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# complete