prev_cmp_testctl.map.qmsg

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 20 12:54:15 2008 " "Info: Processing started: Wed Aug 20 12:54:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fequency -c testctl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fequency -c testctl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testctl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file testctl.v" { { "Info" "ISGN_ENTITY_NAME" "1 testctl " "Info: Found entity 1: testctl" {  } { { "testctl.v" "" { Text "D:/altera/file/fequency/testctl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cout4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cout4.v" { { "Info" "ISGN_ENTITY_NAME" "1 cout4 " "Info: Found entity 1: cout4" {  } { { "cout4.v" "" { Text "D:/altera/file/fequency/cout4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg32b.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file reg32b.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg32b " "Info: Found entity 1: reg32b" {  } { { "reg32b.v" "" { Text "D:/altera/file/fequency/reg32b.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fequency.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fequency.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fequency " "Info: Found entity 1: fequency" {  } { { "fequency.bdf" "" { Schematic "D:/altera/file/fequency/fequency.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file second.v" { { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.v" "" { Text "D:/altera/file/fequency/second.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "second " "Info: Elaborating entity \"second\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "sec_out second.v(6) " "Warning (10755): Verilog HDL warning at second.v(6): assignments to sec_out create a combinational loop" {  } { { "second.v" "" { Text "D:/altera/file/fequency/second.v" 6 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2 " "Info: Implemented 2 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "0 " "Info: Implemented 0 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Peak virtual memory: 158 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 20 12:54:26 2008 " "Info: Processing ended: Wed Aug 20 12:54:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}