testctl.map.summary

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

Analysis & Synthesis Status : Successful - Wed Aug 20 13:01:05 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : testctl
Top-level Entity Name : second
Family : Cyclone II
Total logic elements : 1
    Total combinational functions : 1
    Dedicated logic registers : 0
Total registers : 0
Total pins : 1
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0