cout4.v.bak

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

module cout4(clk, clr, ena, cq, carry_out);
	input clk, clr, ena;
	output carry_out;
	output [3:0] cq;
	
	reg [3:0] cq;
	reg carry_out;
	reg [3:0] precq;
	
	
	
	always @(posedge clk or posedge clr)
		begin
		if(clr)
			precq <= 4'b0;
		else
			if(ena)
				if(precq<10)
					precq <=precq+1'b1;
				else if(precq==10)
					precq <=1'b1;				
				else
					precq <=0;
		end
	
	
	always @(precq)
		begin

		if(precq==10)
			begin
			carry_out <=1;
			cq <=0;
			end
		else
			begin
			carry_out <=0;
			cq <= precq;
			end
		end
endmodule