light.tan.rpt

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真交通灯

; N/A   ; 363.90 MHz ( period = 2.748 ns )               ; current_state.green  ; time[3]              ; clk        ; clk      ; None                        ; None                      ; 2.546 ns                ;
; N/A   ; 363.90 MHz ( period = 2.748 ns )               ; current_state.green  ; time[2]              ; clk        ; clk      ; None                        ; None                      ; 2.546 ns                ;
; N/A   ; 363.90 MHz ( period = 2.748 ns )               ; current_state.green  ; time[0]              ; clk        ; clk      ; None                        ; None                      ; 2.546 ns                ;
; N/A   ; 363.90 MHz ( period = 2.748 ns )               ; current_state.green  ; time[1]              ; clk        ; clk      ; None                        ; None                      ; 2.546 ns                ;
; N/A   ; 363.90 MHz ( period = 2.748 ns )               ; current_state.green  ; time[4]              ; clk        ; clk      ; None                        ; None                      ; 2.546 ns                ;
; N/A   ; 379.79 MHz ( period = 2.633 ns )               ; time[3]              ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 2.431 ns                ;
; N/A   ; 379.79 MHz ( period = 2.633 ns )               ; time[3]              ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 2.431 ns                ;
; N/A   ; 379.79 MHz ( period = 2.633 ns )               ; time[3]              ; current_state.yellow ; clk        ; clk      ; None                        ; None                      ; 2.431 ns                ;
; N/A   ; 386.70 MHz ( period = 2.586 ns )               ; time[0]              ; time[3]              ; clk        ; clk      ; None                        ; None                      ; 2.384 ns                ;
; N/A   ; 386.70 MHz ( period = 2.586 ns )               ; time[0]              ; time[2]              ; clk        ; clk      ; None                        ; None                      ; 2.384 ns                ;
; N/A   ; 386.70 MHz ( period = 2.586 ns )               ; time[0]              ; time[0]              ; clk        ; clk      ; None                        ; None                      ; 2.384 ns                ;
; N/A   ; 386.70 MHz ( period = 2.586 ns )               ; time[0]              ; time[1]              ; clk        ; clk      ; None                        ; None                      ; 2.384 ns                ;
; N/A   ; 386.70 MHz ( period = 2.586 ns )               ; time[0]              ; time[4]              ; clk        ; clk      ; None                        ; None                      ; 2.384 ns                ;
; N/A   ; 390.78 MHz ( period = 2.559 ns )               ; current_state.green  ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 2.357 ns                ;
; N/A   ; 390.78 MHz ( period = 2.559 ns )               ; current_state.green  ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 2.357 ns                ;
; N/A   ; 390.78 MHz ( period = 2.559 ns )               ; current_state.green  ; current_state.yellow ; clk        ; clk      ; None                        ; None                      ; 2.357 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[0]              ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 2.195 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[0]              ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 2.195 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[0]              ; current_state.yellow ; clk        ; clk      ; None                        ; None                      ; 2.195 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; time[3]              ; clk        ; clk      ; None                        ; None                      ; 1.888 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; time[2]              ; clk        ; clk      ; None                        ; None                      ; 1.888 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; time[0]              ; clk        ; clk      ; None                        ; None                      ; 1.888 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; time[1]              ; clk        ; clk      ; None                        ; None                      ; 1.888 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; time[4]              ; clk        ; clk      ; None                        ; None                      ; 1.888 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; time[3]              ; clk        ; clk      ; None                        ; None                      ; 1.728 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; time[2]              ; clk        ; clk      ; None                        ; None                      ; 1.728 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; time[0]              ; clk        ; clk      ; None                        ; None                      ; 1.728 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; time[1]              ; clk        ; clk      ; None                        ; None                      ; 1.728 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; time[4]              ; clk        ; clk      ; None                        ; None                      ; 1.728 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[4]              ; current_state.yellow ; clk        ; clk      ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 1.539 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 1.539 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; time[1]              ; current_state.yellow ; clk        ; clk      ; None                        ; None                      ; 1.539 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; current_state.yellow ; current_state.red    ; clk        ; clk      ; None                        ; None                      ; 0.647 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; current_state.red    ; current_state.green  ; clk        ; clk      ; None                        ; None                      ; 0.646 ns                ;
+-------+------------------------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+----------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To      ; From Clock ;
+-------+--------------+------------+----------------------+---------+------------+
; N/A   ; None         ; 4.983 ns   ; current_state.yellow ; cout[0] ; clk        ;
; N/A   ; None         ; 4.893 ns   ; current_state.green  ; cout[1] ; clk        ;
; N/A   ; None         ; 4.882 ns   ; current_state.red    ; cout[2] ; clk        ;
+-------+--------------+------------+----------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Dec 08 22:08:52 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off light -c light --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 337.27 MHz between source register "time[2]" and destination register "time[3]" (period= 2.965 ns)
    Info: + Longest register to register delay is 2.763 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N7; Fanout = 4; REG Node = 'time[2]'
        Info: 2: + IC(0.428 ns) + CELL(0.454 ns) = 0.882 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'reduce_nor~114'
        Info: 3: + IC(0.318 ns) + CELL(0.340 ns) = 1.540 ns; Loc. = LC_X2_Y1_N1; Fanout = 8; COMB Node = 'reduce_nor~0'
        Info: 4: + IC(0.367 ns) + CELL(0.856 ns) = 2.763 ns; Loc. = LC_X2_Y1_N8; Fanout = 4; REG Node = 'time[3]'
        Info: Total cell delay = 1.650 ns ( 59.72 % )
        Info: Total interconnect delay = 1.113 ns ( 40.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.099 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N8; Fanout = 4; REG Node = 'time[3]'
            Info: Total cell delay = 1.677 ns ( 79.90 % )
            Info: Total interconnect delay = 0.422 ns ( 20.10 % )
        Info: - Longest clock path from clock "clk" to source register is 2.099 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N7; Fanout = 4; REG Node = 'time[2]'
            Info: Total cell delay = 1.677 ns ( 79.90 % )
            Info: Total interconnect delay = 0.422 ns ( 20.10 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "cout[0]" through register "current_state.yellow" is 4.983 ns
    Info: + Longest clock path from clock "clk" to source register is 2.099 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'current_state.yellow'
        Info: Total cell delay = 1.677 ns ( 79.90 % )
        Info: Total interconnect delay = 0.422 ns ( 20.10 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.711 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'current_state.yellow'
        Info: 2: + IC(1.077 ns) + CELL(1.634 ns) = 2.711 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'cout[0]'
        Info: Total cell delay = 1.634 ns ( 60.27 % )
        Info: Total interconnect delay = 1.077 ns ( 39.73 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Dec 08 22:08:52 2007
    Info: Elapsed time: 00:00:01