full_adder.vhd

来自「32位全加器 在querters II 下面运行成功 仿真 验证均已成功」· VHDL 代码 · 共 13 行

library IEEE;
use IEEE.std_logic_1164.all;

entity FULL_ADDER is
        port (X,Y,Cin : In std_logic; Cout, Sum: Out std_logic);
end FULL_ADDER;

architecture behaviour of FULL_ADDER is
begin
Sum  <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end;