mult_add_lh23.tdf

安徽省首届大学生电子设计竞赛

--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Cyclone" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_A2="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" INPUT_REGISTER_B2="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" INPUT_SOURCE_A2="DATAA" INPUT_SOURCE_B0="DATAB" INPUT_SOURCE_B1="DATAB" INPUT_SOURCE_B2="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" MULTIPLIER_REGISTER2="CLOCK0" NUMBER_OF_MULTIPLIERS=3 OUTPUT_REGISTER="CLOCK0" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" WIDTH_A=10 WIDTH_B=4 WIDTH_RESULT=10 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.1 cbx_alt_ded_mult_y 2005:10:01:11:15:32:SJ cbx_altmult_add 2005:09:22:10:39:08:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_padd 2005:08:04:11:57:36:SJ cbx_parallel_add 2003:11:12:11:26:08:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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FUNCTION alt_mac_mult (aclr[3..0], clk[3..0], dataa[DATAA_WIDTH-1..0], datab[DATAB_WIDTH-1..0], ena[3..0], round, saturate, scanina[DATAA_WIDTH-1..0], scaninb[DATAB_WIDTH-1..0], signa, signb, sourcea, sourceb)
WITH ( 	BYPASS_MULTIPLIER,	DATAA_CLEAR,	DATAA_CLOCK,	DATAA_WIDTH,	DATAB_CLEAR,	DATAB_CLOCK,	DATAB_WIDTH,	DYNAMIC_SCAN_CHAIN_SUPPORTED,	EXTRA_OUTPUT_CLEAR,	EXTRA_OUTPUT_CLOCK,	EXTRA_SIGNA_CLEAR,	EXTRA_SIGNA_CLOCK,	EXTRA_SIGNB_CLEAR,	EXTRA_SIGNB_CLOCK,	MULT_CLEAR,	MULT_CLOCK,	MULT_INPUT_A_IS_CONSTANT,	MULT_INPUT_B_IS_CONSTANT,	MULT_MAXIMIZE_SPEED,	MULT_PIPELINE,	MULT_REPRESENTATION_A,	MULT_REPRESENTATION_B,	OUTPUT_CLEAR,	OUTPUT_CLOCK,	OUTPUT_WIDTH,	ROUND_CLEAR,	ROUND_CLOCK,	SATURATE_CLEAR,	SATURATE_CLOCK,	SIGNA_CLEAR,	SIGNA_CLOCK,	SIGNB_CLEAR,	SIGNB_CLOCK,	USING_ROUNDING,	USING_SATURATION) 
RETURNS ( dataout[OUTPUT_WIDTH-1..0], scanouta[DATAA_WIDTH-1..0], scanoutb[DATAB_WIDTH-1..0]);
PARAMETERS
(
	DATAB_WIDTH = 1,
	DATAC_WIDTH = 1,
	DATAD_WIDTH = 1
);
FUNCTION alt_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[DATAA_WIDTH-1..0], datab[DATAB_WIDTH-1..0], datac[DATAC_WIDTH-1..0], datad[DATAD_WIDTH-1..0], ena[3..0], mode0, mode1, multabsaturate, multcdsaturate, round0, round1, saturate, saturate1, signa, signb, zeroacc, zeroacc1)
WITH ( 	ADDNSUB0_CLEAR,	ADDNSUB0_CLOCK,	ADDNSUB0_PIPELINE_CLEAR,	ADDNSUB0_PIPELINE_CLOCK,	ADDNSUB1_CLEAR,	ADDNSUB1_CLOCK,	ADDNSUB1_PIPELINE_CLEAR,	ADDNSUB1_PIPELINE_CLOCK,	DATAA_FORCED_TO_ZERO,	DATAA_WIDTH,	DATAB_WIDTH,	DATAC_FORCED_TO_ZERO,	DATAC_WIDTH,	DATAD_WIDTH,	LOADABLE_ACCUM_SUPPORTED,	MODE0_CLEAR,	MODE0_CLOCK,	MODE0_PIPELINE_CLEAR,	MODE0_PIPELINE_CLOCK,	MODE1_CLEAR,	MODE1_CLOCK,	MODE1_PIPELINE_CLEAR,	MODE1_PIPELINE_CLOCK,	MULTABSATURATE_CLEAR,	MULTABSATURATE_CLOCK,	MULTABSATURATE_PIPELINE_CLEAR,	MULTABSATURATE_PIPELINE_CLOCK,	MULTCDSATURATE_CLEAR,	MULTCDSATURATE_CLOCK,	MULTCDSATURATE_PIPELINE_CLEAR,	MULTCDSATURATE_PIPELINE_CLOCK,	OPERATION_MODE,	OUTPUT_CLEAR,	OUTPUT_CLOCK,	OUTPUT_WIDTH,	ROUND0_CLEAR,	ROUND0_CLOCK,	ROUND0_PIPELINE_CLEAR,	ROUND0_PIPELINE_CLOCK,	ROUND1_CLEAR,	ROUND1_CLOCK,	ROUND1_PIPELINE_CLEAR,	ROUND1_PIPELINE_CLOCK,	SATURATE_CLEAR,	SATURATE_CLOCK,	SATURATE_PIPELINE_CLEAR,	SATURATE_PIPELINE_CLOCK,	SIGNA_CLEAR,	SIGNA_CLOCK,	SIGNA_PIPELINE_CLEAR,	SIGNA_PIPELINE_CLOCK,	SIGNB_CLEAR,	SIGNB_CLOCK,	SIGNB_PIPELINE_CLEAR,	SIGNB_PIPELINE_CLOCK,	USING_LOADABLE_ACCUM,	USING_MULT_SATURATION,	USING_ROUNDING,	USING_SATURATION,	ZEROACC_CLEAR,	ZEROACC_CLOCK,	ZEROACC_PIPELINE_CLEAR,	ZEROACC_PIPELINE_CLOCK) 
RETURNS ( accoverflow, dataout[OUTPUT_WIDTH-1..0]);

--synthesis_resources = alt_mac_mult 3 alt_mac_out 1 
SUBDESIGN mult_add_lh23
( 
	clock0	:	input;
	dataa[29..0]	:	input;
	datab[11..0]	:	input;
	result[9..0]	:	output;
) 
VARIABLE 
	mac_mult1 : alt_mac_mult
		WITH (
			DATAA_CLEAR = "A_3",
			DATAA_CLOCK = "A_0",
			DATAA_WIDTH = 10,
			DATAB_CLEAR = "A_3",
			DATAB_CLOCK = "A_0",
			DATAB_WIDTH = 4,
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 14
		);
	mac_mult2 : alt_mac_mult
		WITH (
			DATAA_CLEAR = "A_3",
			DATAA_CLOCK = "A_0",
			DATAA_WIDTH = 10,
			DATAB_CLEAR = "A_3",
			DATAB_CLOCK = "A_0",
			DATAB_WIDTH = 4,
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 14
		);
	mac_mult3 : alt_mac_mult
		WITH (
			DATAA_CLEAR = "A_3",
			DATAA_CLOCK = "A_0",
			DATAA_WIDTH = 10,
			DATAB_CLEAR = "A_3",
			DATAB_CLOCK = "A_0",
			DATAB_WIDTH = 4,
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 14
		);
	mac_out4 : alt_mac_out
		WITH (
			DATAA_WIDTH = 14,
			DATAB_WIDTH = 14,
			DATAC_WIDTH = 14,
			DATAD_WIDTH = 14,
			OPERATION_MODE = "TWO_LEVEL_ADDER",
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 16
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	aclr3	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[29..0]	: WIRE;
	datab_bus[11..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( dataa_bus[9..0]);
	mac_mult1.datab[] = ( datab_bus[3..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_mult2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult2.dataa[] = ( dataa_bus[19..10]);
	mac_mult2.datab[] = ( datab_bus[7..4]);
	mac_mult2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult2.signa = B"0";
	mac_mult2.signb = B"0";
	mac_mult3.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult3.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult3.dataa[] = ( dataa_bus[29..20]);
	mac_mult3.datab[] = ( datab_bus[11..8]);
	mac_mult3.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult3.signa = B"0";
	mac_mult3.signb = B"0";
	mac_out4.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out4.addnsub0 = B"1";
	mac_out4.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out4.dataa[] = ( mac_mult1.dataout[13..0]);
	mac_out4.datab[] = ( mac_mult2.dataout[13..0]);
	mac_out4.datac[] = ( mac_mult3.dataout[13..0]);
	mac_out4.datad[] = ( B"00000000000000");
	mac_out4.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out4.signa = B"0";
	mac_out4.signb = B"0";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	aclr3 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[29..0]);
	datab_bus[] = ( datab[11..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[9..0] = mac_out4.dataout[9..0];
END;
--VALID FILE