dds_sin.map.qmsg

安徽省首届大学生电子设计竞赛

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ll.vhd 2 1 " "Warning: Using design file ll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ll-SYN " "Info: Found design unit 1: ll-SYN" {  } { { "ll.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ll.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ll " "Info: Found entity 1: ll" {  } { { "ll.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ll mul_6:mul\|ll:u2 " "Info: Elaborating entity \"ll\" for hierarchy \"mul_6:mul\|ll:u2\"" {  } { { "mul_6.vhd" "u2" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component " "Info: Elaborating entity \"lpm_divide\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\"" {  } { { "ll.vhd" "lpm_divide_component" { Text "D:/VHDL/copy/dds_sin_std4/ll.vhd" 78 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_k5j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_k5j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_k5j " "Info: Found entity 1: lpm_divide_k5j" {  } { { "db/lpm_divide_k5j.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/lpm_divide_k5j.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_k5j mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated " "Info: Elaborating entity \"lpm_divide_k5j\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf" 145 9 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_7jg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7jg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_7jg " "Info: Found entity 1: sign_div_unsign_7jg" {  } { { "db/sign_div_unsign_7jg.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/sign_div_unsign_7jg.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_7jg mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider " "Info: Elaborating entity \"sign_div_unsign_7jg\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\"" {  } { { "db/lpm_divide_k5j.tdf" "divider" { Text "D:/VHDL/copy/dds_sin_std4/db/lpm_divide_k5j.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_jod.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_jod.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_jod " "Info: Found entity 1: alt_u_div_jod" {  } { { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_jod mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider " "Info: Elaborating entity \"alt_u_div_jod\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\"" {  } { { "db/sign_div_unsign_7jg.tdf" "divider" { Text "D:/VHDL/copy/dds_sin_std4/db/sign_div_unsign_7jg.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ke8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ke8 " "Info: Found entity 1: add_sub_ke8" {  } { { "db/add_sub_ke8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_ke8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_ke8 mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_ke8:add_sub_0 " "Info: Elaborating entity \"add_sub_ke8\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_ke8:add_sub_0\"" {  } { { "db/alt_u_div_jod.tdf" "add_sub_0" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_le8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_le8 " "Info: Found entity 1: add_sub_le8" {  } { { "db/add_sub_le8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_le8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_le8 mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_le8:add_sub_1 " "Info: Elaborating entity \"add_sub_le8\" for hierarchy \"mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated