dds_sin.map.qmsg

安徽省首届大学生电子设计竞赛

{ "Warning" "WSGN_SEARCH_FILE" "mul_6.vhd 2 1 " "Warning: Using design file mul_6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mul_6-behave " "Info: Found design unit 1: mul_6-behave" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mul_6 " "Info: Found entity 1: mul_6" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mul_6 mul_6:mul " "Info: Elaborating entity \"mul_6\" for hierarchy \"mul_6:mul\"" {  } { { "dds_sin.vhd" "mul" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 121 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "numer1 mul_6.vhd(25) " "Info (10035): Verilog HDL or VHDL information at mul_6.vhd(25): object \"numer1\" declared but not used" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 25 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "denom1 mul_6.vhd(26) " "Info (10035): Verilog HDL or VHDL information at mul_6.vhd(26): object \"denom1\" declared but not used" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 26 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "bbb mul_6.vhd(56) " "Warning (10540): VHDL Signal Declaration warning at mul_6.vhd(56): used explicit default value for signal \"bbb\" because signal was never assigned a value" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 56 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "remain1 mul_6.vhd(57) " "Warning (10036): Verilog HDL or VHDL warning at mul_6.vhd(57): object \"remain1\" assigned a value but never read" {  } { { "mul_6.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 57 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "kk.vhd 2 1 " "Warning: Using design file kk.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 kk-SYN " "Info: Found design unit 1: kk-SYN" {  } { { "kk.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/kk.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 kk " "Info: Found entity 1: kk" {  } { { "kk.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/kk.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "kk mul_6:mul\|kk:u1 " "Info: Elaborating entity \"kk\" for hierarchy \"mul_6:mul\|kk:u1\"" {  } { { "mul_6.vhd" "u1" { Text "D:/VHDL/copy/dds_sin_std4/mul_6.vhd" 59 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altmult_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altmult_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altmult_add " "Info: Found entity 1: altmult_add" {  } { { "altmult_add.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altmult_add.tdf" 298 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component " "Info: Elaborating entity \"altmult_add\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\"" {  } { { "kk.vhd" "ALTMULT_ADD_component" { Text "D:/VHDL/copy/dds_sin_std4/kk.vhd" 141 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_rh23.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_rh23.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_rh23 " "Info: Found entity 1: mult_add_rh23" {  } { { "db/mult_add_rh23.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/mult_add_rh23.tdf" 34 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_rh23 mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated " "Info: Elaborating entity \"mult_add_rh23\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altmult_add.tdf" 478 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/alt_mac_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/alt_mac_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mac_mult " "Info: Found entity 1: alt_mac_mult" {  } { { "alt_mac_mult.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_mult.tdf" 142 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mac_mult mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1 " "Info: Elaborating entity \"alt_mac_mult\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1\"" {  } { { "db/mult_add_rh23.tdf" "mac_mult1" { Text "D:/VHDL/copy/dds_sin_std4/db/mult_add_rh23.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1\|lpm_mult:mult " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1\|lpm_mult:mult\"" {  } { { "alt_mac_mult.tdf" "mult" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_mult.tdf" 273 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_4261.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_4261.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_4261 " "Info: Found entity 1: mult_4261" {  } { { "db/mult_4261.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/mult_4261.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_4261 mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1\|lpm_mult:mult\|mult_4261:auto_generated " "Info: Elaborating entity \"mult_4261\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_mult:mac_mult1\|lpm_mult:mult\|mult_4261:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 372 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mac_out " "Info: Found entity 1: alt_mac_out" {  } { { "alt_mac_out.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf" 203 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mac_out mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4 " "Info: Elaborating entity \"alt_mac_out\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\"" {  } { { "db/mult_add_rh23.tdf" "mac_out4" { Text "D:/VHDL/copy/dds_sin_std4/db/mult_add_rh23.tdf" 78 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:addsub0 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:addsub0\"" {  } { { "alt_mac_out.tdf" "addsub0" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf" 467 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/alt_stratix_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/alt_stratix_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_stratix_add_sub " "Info: Found entity 1: alt_stratix_add_sub" {  } { { "alt_stratix_add_sub.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/alt_stratix_add_sub.tdf" 92 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_stratix_add_sub mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:addsub0\|alt_stratix_add_sub:stratix_adder " "Info: Elaborating entity \"alt_stratix_add_sub\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:addsub0\|alt_stratix_add_sub:stratix_adder\"" {  } { { "lpm_add_sub.tdf" "stratix_adder" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 138 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|lpm_add_sub:sum\"" {  } { { "alt_mac_out.tdf" "sum" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf" 485 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}