dds_sin.map.qmsg

安徽省首届大学生电子设计竞赛

{ "Info" "ISGN_MEGAFN_DESCENDANT" "ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom ddsc:i_dds\|LPM_ROM:i_rom2 " "Info: Issued messages during elaboration of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\", which is child of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom2\"" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 146 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddsc:i_dds\|LPM_ROM:i_rom2 " "Info: Instantiated megafunction \"ddsc:i_dds\|LPM_ROM:i_rom2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 10 " "Info: Parameter \"LPM_WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NUMWORDS 0 " "Info: Parameter \"LPM_NUMWORDS\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL UNREGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA REGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE fangbo.mif " "Info: Parameter \"LPM_FILE\" = \"fangbo.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ROM " "Info: Parameter \"LPM_TYPE\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INTENDED_DEVICE_FAMILY UNUSED " "Info: Parameter \"INTENDED_DEVICE_FAMILY\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 9 downto 0 " "Info: Parameter \" constraint(address)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(q) 9 downto 0 " "Info: Parameter \" constraint(q)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 146 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different. " "Warning: Assertion warning: Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different." {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 194 2 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 143 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ITDFX_ASSERTION" "Clocko port is used as clock for the address input port " "Info: Assertion information: Clocko port is used as clock for the address input port" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 283 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 143 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion information: %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 102 8 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5to.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5to.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5to " "Info: Found entity 1: altsyncram_5to" {  } { { "db/altsyncram_5to.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_5to.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5to ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\|altsyncram:rom_block\|altsyncram_5to:auto_generated " "Info: Elaborating entity \"altsyncram_5to\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\|altsyncram:rom_block\|altsyncram_5to:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM ddsc:i_dds\|LPM_ROM:i_rom3 " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom3\"" {  } { { "ddsc.vhd" "i_rom3" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 150 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom ddsc:i_dds\|LPM_ROM:i_rom3 " "Info: Issued messages during elaboration of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\", which is child of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom3\"" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 150 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddsc:i_dds\|LPM_ROM:i_rom3 " "Info: Instantiated megafunction \"ddsc:i_dds\|LPM_ROM:i_rom3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 10 " "Info: Parameter \"LPM_WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NUMWORDS 0 " "Info: Parameter \"LPM_NUMWORDS\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL UNREGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA REGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE sanjiao.mif " "Info: Parameter \"LPM_FILE\" = \"sanjiao.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ROM " "Info: Parameter \"LPM_TYPE\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INTENDED_DEVICE_FAMILY UNUSED " "Info: Parameter \"INTENDED_DEVICE_FAMILY\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 9 downto 0 " "Info: Parameter \" constraint(address)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(q) 9 downto 0 " "Info: Parameter \" constraint(q)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 150 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different. " "Warning: Assertion warning: Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different." {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 194 2 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 147 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ITDFX_ASSERTION" "Clocko port is used as clock for the address input port " "Info: Assertion information: Clocko port is used as clock for the address input port" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 283 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 147 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion information: %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 102 8 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_t0p.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t0p.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_t0p " "Info: Found entity 1: altsyncram_t0p" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_t0p ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated " "Info: Elaborating entity \"altsyncram_t0p\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM ddsc:i_dds\|LPM_ROM:i_rom4 " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom4\"" {  } { { "ddsc.vhd" "i_rom4" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 156 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom ddsc:i_dds\|LPM_ROM:i_rom4 " "Info: Issued messages during elaboration of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\", which is child of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom4\"" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 156 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddsc:i_dds\|LPM_ROM:i_rom4 " "Info: Instantiated megafunction \"ddsc:i_dds\|LPM_ROM:i_rom4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 10 " "Info: Parameter \"LPM_WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NUMWORDS 0 " "Info: Parameter \"LPM_NUMWORDS\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL UNREGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA REGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE sinbo1.mif " "Info: Parameter \"LPM_FILE\" = \"sinbo1.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ROM " "Info: Parameter \"LPM_TYPE\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INTENDED_DEVICE_FAMILY UNUSED " "Info: Parameter \"INTENDED_DEVICE_FAMILY\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 9 downto 0 " "Info: Parameter \" constraint(address)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(q) 9 downto 0 " "Info: Parameter \" constraint(q)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 156 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different. " "Warning: Assertion warning: Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different." {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 194 2 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 153 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ITDFX_ASSERTION" "Clocko port is used as clock for the address input port " "Info: Assertion information: Clocko port is used as clock for the address input port" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 283 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 153 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion information: %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 102 8 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4so.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4so.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4so " "Info: Found entity 1: altsyncram_4so" {  } { { "db/altsyncram_4so.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_4so.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4so ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\|altsyncram:rom_block\|altsyncram_4so:auto_generated " "Info: Elaborating entity \"altsyncram_4so\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom4\|altrom:srom\|altsyncram:rom_block\|altsyncram_4so:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}