dds_sin.map.qmsg

安徽省首届大学生电子设计竞赛

{ "Warning" "WSGN_SEARCH_FILE" "ppl2_5.vhd 2 1 " "Warning: Using design file ppl2_5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ppl2_5-SYN " "Info: Found design unit 1: ppl2_5-SYN" {  } { { "ppl2_5.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ppl2_5.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ppl2_5 " "Info: Found entity 1: ppl2_5" {  } { { "ppl2_5.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ppl2_5.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ppl2_5 ppl2_5:ppl " "Info: Elaborating entity \"ppl2_5\" for hierarchy \"ppl2_5:ppl\"" {  } { { "dds_sin.vhd" "ppl" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 114 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ppl2_5:ppl\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"ppl2_5:ppl\|altpll:altpll_component\"" {  } { { "ppl2_5.vhd" "altpll_component" { Text "D:/VHDL/copy/dds_sin_std4/ppl2_5.vhd" 86 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddsc ddsc:i_dds " "Info: Elaborating entity \"ddsc\" for hierarchy \"ddsc:i_dds\"" {  } { { "dds_sin.vhd" "i_dds" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 115 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "romaddr2 ddsc.vhd(36) " "Warning (10036): Verilog HDL or VHDL warning at ddsc.vhd(36): object \"romaddr2\" assigned a value but never read" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 36 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ddsout5 ddsc.vhd(47) " "Info (10035): Verilog HDL or VHDL information at ddsc.vhd(47): object \"ddsout5\" declared but not used" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 47 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "tmp3 ddsc.vhd(54) " "Info (10035): Verilog HDL or VHDL information at ddsc.vhd(54): object \"tmp3\" declared but not used" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ddsout1 ddsc.vhd(166) " "Warning (10492): VHDL Process Statement warning at ddsc.vhd(166): signal \"ddsout1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 166 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ddsout4 ddsc.vhd(166) " "Warning (10492): VHDL Process Statement warning at ddsc.vhd(166): signal \"ddsout4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 166 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ss_tmp ddsc.vhd(167) " "Warning (10492): VHDL Process Statement warning at ddsc.vhd(167): signal \"ss_tmp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 167 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 41 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM ddsc:i_dds\|LPM_ROM:i_rom1 " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom1\"" {  } { { "ddsc.vhd" "i_rom1" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 142 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom ddsc:i_dds\|LPM_ROM:i_rom1 " "Info: Issued messages during elaboration of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\", which is child of megafunction \"ddsc:i_dds\|LPM_ROM:i_rom1\"" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 142 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddsc:i_dds\|LPM_ROM:i_rom1 " "Info: Instantiated megafunction \"ddsc:i_dds\|LPM_ROM:i_rom1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 10 " "Info: Parameter \"LPM_WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NUMWORDS 0 " "Info: Parameter \"LPM_NUMWORDS\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL UNREGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA REGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE sinbo.mif " "Info: Parameter \"LPM_FILE\" = \"sinbo.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ROM " "Info: Parameter \"LPM_TYPE\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INTENDED_DEVICE_FAMILY UNUSED " "Info: Parameter \"INTENDED_DEVICE_FAMILY\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 9 downto 0 " "Info: Parameter \" constraint(address)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(q) 9 downto 0 " "Info: Parameter \" constraint(q)\" = \"9 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 142 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different. " "Warning: Assertion warning: Can't convert ROM for Cyclone device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different." {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 194 2 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 139 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ITDFX_ASSERTION" "Clocko port is used as clock for the address input port " "Info: Assertion information: Clocko port is used as clock for the address input port" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 283 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 139 -1 0 } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 104 -1 0 } }  } 0 0 "Assertion information: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/quartus51/libraries/megafunctions/altrom.tdf" 102 8 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jqo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jqo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jqo " "Info: Found entity 1: altsyncram_jqo" {  } { { "db/altsyncram_jqo.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_jqo.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jqo ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated " "Info: Elaborating entity \"altsyncram_jqo\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM ddsc:i_dds\|LPM_ROM:i_rom2 " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom2\"" {  } { { "ddsc.vhd" "i_rom2" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 146 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"ddsc:i_dds\|LPM_ROM:i_rom2\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "e:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 58 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}