dds_sin.map.qmsg

安徽省首届大学生电子设计竞赛

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 12 15:09:55 2006 " "Info: Processing started: Tue Sep 12 15:09:55 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds_sin -c dds_sin " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds_sin -c dds_sin" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds_sin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds_sin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dds_sin-behave " "Info: Found design unit 1: dds_sin-behave" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dds_sin " "Info: Found entity 1: dds_sin" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddsc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ddsc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ddsc-behave " "Info: Found design unit 1: ddsc-behave" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ddsc " "Info: Found entity 1: ddsc" {  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds_sin " "Info: Elaborating entity \"dds_sin\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "tmp dds_sin.vhd(88) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(88): object \"tmp\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 88 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "aa1 dds_sin.vhd(89) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(89): object \"aa1\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 89 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "bb1 dds_sin.vhd(89) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(89): object \"bb1\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 89 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cc1 dds_sin.vhd(89) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(89): object \"cc1\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 89 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "Q2 dds_sin.vhd(102) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(102): object \"Q2\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 102 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "COUT dds_sin.vhd(105) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(105): object \"COUT\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 105 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cclk dds_sin.vhd(109) " "Info (10035): Verilog HDL or VHDL information at dds_sin.vhd(109): object \"cclk\" declared but not used" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 109 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ccclk dds_sin.vhd(161) " "Warning (10492): VHDL Process Statement warning at dds_sin.vhd(161): signal \"ccclk\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cmp_sel dds_sin.vhd(190) " "Warning (10492): VHDL Process Statement warning at dds_sin.vhd(190): signal \"cmp_sel\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 190 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ddsout_cmp1 dds_sin.vhd(191) " "Warning (10492): VHDL Process Statement warning at dds_sin.vhd(191): signal \"ddsout_cmp1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 191 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ddsout_145 dds_sin.vhd(193) " "Warning (10492): VHDL Process Statement warning at dds_sin.vhd(193): signal \"ddsout_145\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 193 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[15\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[15\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[14\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[14\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[13\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[13\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[12\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[12\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[11\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[11\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[10\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[10\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[9\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[9\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "phaseind\[8\] X dds_sin.vhd(86) " "Warning (10030): Tied undriven net \"phaseind\[8\]\" at dds_sin.vhd(86) to X" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 86 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}