dds_sin.map.eqn

安徽省首届大学生电子设计竞赛

--K1_q_a[3] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[3]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[3]_PORT_A_address_reg = DFFE(K1_q_a[3]_PORT_A_address, K1_q_a[3]_clock_0, , , );
K1_q_a[3]_clock_0 = PB1__clk0;
K1_q_a[3]_PORT_A_data_out = MEMORY(, , K1_q_a[3]_PORT_A_address_reg, , , , , , K1_q_a[3]_clock_0, , , , , );
K1_q_a[3] = K1_q_a[3]_PORT_A_data_out[0];


--A1L79 is ddsout_rom~779
--operation mode is normal

A1L79 = A1L60 & (A1L78 & (K1_q_a[3]) # !A1L78 & L1_q_a[3]) # !A1L60 & (A1L78);


--J1_q_a[4] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[4]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[4]_PORT_A_address_reg = DFFE(J1_q_a[4]_PORT_A_address, J1_q_a[4]_clock_0, , , );
J1_q_a[4]_clock_0 = PB1__clk0;
J1_q_a[4]_PORT_A_data_out = MEMORY(, , J1_q_a[4]_PORT_A_address_reg, , , , , , J1_q_a[4]_clock_0, , , , , );
J1_q_a[4] = J1_q_a[4]_PORT_A_data_out[0];


--B1L140 is ddsc:i_dds|add~1301
--operation mode is arithmetic

B1L140_carry_eqn = B1L139;
B1L140 = M1_q_a[5] $ J1_q_a[5] $ B1L140_carry_eqn;

--B1L141 is ddsc:i_dds|add~1303
--operation mode is arithmetic

B1L141 = CARRY(M1_q_a[5] & !J1_q_a[5] & !B1L139 # !M1_q_a[5] & (!B1L139 # !J1_q_a[5]));


--L1_q_a[4] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[4]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[4]_PORT_A_address_reg = DFFE(L1_q_a[4]_PORT_A_address, L1_q_a[4]_clock_0, , , );
L1_q_a[4]_clock_0 = PB1__clk0;
L1_q_a[4]_PORT_A_data_out = MEMORY(, , L1_q_a[4]_PORT_A_address_reg, , , , , , L1_q_a[4]_clock_0, , , , , );
L1_q_a[4] = L1_q_a[4]_PORT_A_data_out[0];


--A1L80 is ddsout_rom~781
--operation mode is normal

A1L80 = sselect[0] & (B1L140 # !sselect[1]) # !sselect[0] & sselect[1] & (L1_q_a[4]);


--K1_q_a[4] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[4]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[4]_PORT_A_address_reg = DFFE(K1_q_a[4]_PORT_A_address, K1_q_a[4]_clock_0, , , );
K1_q_a[4]_clock_0 = PB1__clk0;
K1_q_a[4]_PORT_A_data_out = MEMORY(, , K1_q_a[4]_PORT_A_address_reg, , , , , , K1_q_a[4]_clock_0, , , , , );
K1_q_a[4] = K1_q_a[4]_PORT_A_data_out[0];


--A1L81 is ddsout_rom~782
--operation mode is normal

A1L81 = sselect[1] & (A1L80) # !sselect[1] & (A1L80 & (K1_q_a[4]) # !A1L80 & J1_q_a[4]);


--L1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[5]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[5]_PORT_A_address_reg = DFFE(L1_q_a[5]_PORT_A_address, L1_q_a[5]_clock_0, , , );
L1_q_a[5]_clock_0 = PB1__clk0;
L1_q_a[5]_PORT_A_data_out = MEMORY(, , L1_q_a[5]_PORT_A_address_reg, , , , , , L1_q_a[5]_clock_0, , , , , );
L1_q_a[5] = L1_q_a[5]_PORT_A_data_out[0];


--B1L142 is ddsc:i_dds|add~1306
--operation mode is arithmetic

B1L142_carry_eqn = B1L141;
B1L142 = M1_q_a[6] $ J1_q_a[6] $ !B1L142_carry_eqn;

--B1L143 is ddsc:i_dds|add~1308
--operation mode is arithmetic

B1L143 = CARRY(M1_q_a[6] & (J1_q_a[6] # !B1L141) # !M1_q_a[6] & J1_q_a[6] & !B1L141);


--J1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[5]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[5]_PORT_A_address_reg = DFFE(J1_q_a[5]_PORT_A_address, J1_q_a[5]_clock_0, , , );
J1_q_a[5]_clock_0 = PB1__clk0;
J1_q_a[5]_PORT_A_data_out = MEMORY(, , J1_q_a[5]_PORT_A_address_reg, , , , , , J1_q_a[5]_clock_0, , , , , );
J1_q_a[5] = J1_q_a[5]_PORT_A_data_out[0];


--A1L82 is ddsout_rom~784
--operation mode is normal

A1L82 = sselect[0] & (B1L142 # !sselect[1]) # !sselect[0] & !sselect[1] & (J1_q_a[5]);


--K1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[5]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[5]_PORT_A_address_reg = DFFE(K1_q_a[5]_PORT_A_address, K1_q_a[5]_clock_0, , , );
K1_q_a[5]_clock_0 = PB1__clk0;
K1_q_a[5]_PORT_A_data_out = MEMORY(, , K1_q_a[5]_PORT_A_address_reg, , , , , , K1_q_a[5]_clock_0, , , , , );
K1_q_a[5] = K1_q_a[5]_PORT_A_data_out[0];


--A1L83 is ddsout_rom~785
--operation mode is normal

A1L83 = A1L60 & (A1L82 & (K1_q_a[5]) # !A1L82 & L1_q_a[5]) # !A1L60 & (A1L82);


--J1_q_a[6] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[6]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[6]_PORT_A_address_reg = DFFE(J1_q_a[6]_PORT_A_address, J1_q_a[6]_clock_0, , , );
J1_q_a[6]_clock_0 = PB1__clk0;
J1_q_a[6]_PORT_A_data_out = MEMORY(, , J1_q_a[6]_PORT_A_address_reg, , , , , , J1_q_a[6]_clock_0, , , , , );
J1_q_a[6] = J1_q_a[6]_PORT_A_data_out[0];


--B1L144 is ddsc:i_dds|add~1311
--operation mode is arithmetic

B1L144_carry_eqn = B1L143;
B1L144 = M1_q_a[7] $ J1_q_a[7] $ B1L144_carry_eqn;

--B1L145 is ddsc:i_dds|add~1313
--operation mode is arithmetic

B1L145 = CARRY(M1_q_a[7] & !J1_q_a[7] & !B1L143 # !M1_q_a[7] & (!B1L143 # !J1_q_a[7]));


--L1_q_a[6] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[6]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[6]_PORT_A_address_reg = DFFE(L1_q_a[6]_PORT_A_address, L1_q_a[6]_clock_0, , , );
L1_q_a[6]_clock_0 = PB1__clk0;
L1_q_a[6]_PORT_A_data_out = MEMORY(, , L1_q_a[6]_PORT_A_address_reg, , , , , , L1_q_a[6]_clock_0, , , , , );
L1_q_a[6] = L1_q_a[6]_PORT_A_data_out[0];


--A1L84 is ddsout_rom~787
--operation mode is normal

A1L84 = sselect[0] & (B1L144 # !sselect[1]) # !sselect[0] & sselect[1] & (L1_q_a[6]);


--K1_q_a[6] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[6]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[6]_PORT_A_address_reg = DFFE(K1_q_a[6]_PORT_A_address, K1_q_a[6]_clock_0, , , );
K1_q_a[6]_clock_0 = PB1__clk0;
K1_q_a[6]_PORT_A_data_out = MEMORY(, , K1_q_a[6]_PORT_A_address_reg, , , , , , K1_q_a[6]_clock_0, , , , , );
K1_q_a[6] = K1_q_a[6]_PORT_A_data_out[0];


--A1L85 is ddsout_rom~788
--operation mode is normal

A1L85 = sselect[1] & (A1L84) # !sselect[1] & (A1L84 & (K1_q_a[6]) # !A1L84 & J1_q_a[6]);


--L1_q_a[7] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[7]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_clock_0 = PB1__clk0;
L1_q_a[7]_PORT_A_data_out = MEMORY(, , L1_q_a[7]_PORT_A_address_reg, , , , , , L1_q_a[7]_clock_0, , , , , );
L1_q_a[7] = L1_q_a[7]_PORT_A_data_out[0];


--B1L146 is ddsc:i_dds|add~1316
--operation mode is arithmetic

B1L146_carry_eqn = B1L145;
B1L146 = M1_q_a[8] $ J1_q_a[8] $ !B1L146_carry_eqn;

--B1L147 is ddsc:i_dds|add~1318
--operation mode is arithmetic

B1L147 = CARRY(M1_q_a[8] & (J1_q_a[8] # !B1L145) # !M1_q_a[8] & J1_q_a[8] & !B1L145);


--J1_q_a[7] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[7]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[7]_PORT_A_address_reg = DFFE(J1_q_a[7]_PORT_A_address, J1_q_a[7]_clock_0, , , );
J1_q_a[7]_clock_0 = PB1__clk0;
J1_q_a[7]_PORT_A_data_out = MEMORY(, , J1_q_a[7]_PORT_A_address_reg, , , , , , J1_q_a[7]_clock_0, , , , , );
J1_q_a[7] = J1_q_a[7]_PORT_A_data_out[0];


--A1L86 is ddsout_rom~790
--operation mode is normal

A1L86 = sselect[0] & (B1L146 # !sselect[1]) # !sselect[0] & !sselect[1] & (J1_q_a[7]);


--K1_q_a[7] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[7]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[7]_PORT_A_address_reg = DFFE(K1_q_a[7]_PORT_A_address, K1_q_a[7]_clock_0, , , );
K1_q_a[7]_clock_0 = PB1__clk0;
K1_q_a[7]_PORT_A_data_out = MEMORY(, , K1_q_a[7]_PORT_A_address_reg, , , , , , K1_q_a[7]_clock_0, , , , , );
K1_q_a[7] = K1_q_a[7]_PORT_A_data_out[0];


--A1L87 is ddsout_rom~791
--operation mode is normal

A1L87 = A1L60 & (A1L86 & (K1_q_a[7]) # !A1L86 & L1_q_a[7]) # !A1L60 & (A1L86);


--J1_q_a[8] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[8]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[8]_PORT_A_address_reg = DFFE(J1_q_a[8]_PORT_A_address, J1_q_a[8]_clock_0, , , );
J1_q_a[8]_clock_0 = PB1__clk0;
J1_q_a[8]_PORT_A_data_out = MEMORY(, , J1_q_a[8]