dds_sin.tan.rpt

安徽省首届大学生电子设计竞赛

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                     ; Actual Time                                    ; From                                                                                                                     ; To                                                                                                                 ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                              ; 10.460 ns                                      ; sel[0]                                                                                                                   ; freqind[17]                                                                                                        ; --                                       ; sysclk                                   ; 0            ;
; Worst-case tco                                          ; N/A       ; None                              ; 13.407 ns                                      ; count[5]                                                                                                                 ; amp_out[5]                                                                                                         ; amp                                      ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                              ; 5.013 ns                                       ; sysclk                                                                                                                   ; dclk                                                                                                               ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A       ; None                              ; -4.395 ns                                      ; RD                                                                                                                       ; DIN[5]                                                                                                             ; --                                       ; sysclk                                   ; 0            ;
; Clock Setup: 'sysclk'                                   ; -9.605 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ; ddsout_rom[8]                                                                                                      ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; sysclk                                   ; 1134         ;
; Clock Setup: 'ppl2_5:ppl|altpll:altpll_component|_clk0' ; -0.244 ns ; 250.00 MHz ( period = 4.000 ns )  ; 235.63 MHz ( period = 4.244 ns )               ; QRD[3]                                                                                                                   ; QRD[0]                                                                                                             ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 30           ;
; Clock Setup: 'cc'                                       ; N/A       ; None                              ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; ddsc:i_dds|cccnt1[1]                                                                                                     ; ddsc:i_dds|cccnt1[3]                                                                                               ; cc                                       ; cc                                       ; 0            ;
; Clock Setup: 'aa'                                       ; N/A       ; None                              ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; ddsc:i_dds|aacnt1[0]                                                                                                     ; ddsc:i_dds|aacnt1[1]                                                                                               ; aa                                       ; aa                                       ; 0            ;
; Clock Setup: 'bb'                                       ; N/A       ; None                              ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; ddsc:i_dds|bbcnt1[2]                                                                                                     ; ddsc:i_dds|bbcnt1[3]                                                                                               ; bb                                       ; bb                                       ; 0            ;
; Clock Setup: 'amp'                                      ; N/A       ; None                              ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1]                                                                                                                 ; count[5]                                                                                                           ; amp                                      ; amp                                      ; 0            ;
; Clock Hold: 'ppl2_5:ppl|altpll:altpll_component|_clk0'  ; -0.786 ns ; 250.00 MHz ( period = 4.000 ns )  ; N/A                                            ; ddsout_rom[3]                                                                                                            ; DIN[3]                                                                                                             ; sysclk                                   ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 5            ;
; Clock Hold: 'sysclk'                                    ; 1.787 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult1|dataa_n[1]         ; mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult1|dataout_n[0] ; sysclk                                   ; sysclk                                   ; 0            ;
; Total number of failed paths                            ;           ;                                   ;                                                ;                                                                                                                          ;                                                                                                                    ;                                          ;                                          ; 1169         ;
+---------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+