dds_sin.sim.rpt

安徽省首届大学生电子设计竞赛

; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;       2.74 % ;
; Total nodes checked                                 ; 438          ;
; Total output ports checked                          ; 730          ;
; Total output ports with complete 1/0-value coverage ; 20           ;
; Total output ports with no 1/0-value coverage       ; 710          ;
; Total output ports with no 1-value coverage         ; 710          ;
; Total output ports with no 0-value coverage         ; 710          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                            ;
+---------------------+-------------------------------+------------------+
; Node Name           ; Output Port Name              ; Output Port Type ;
+---------------------+-------------------------------+------------------+
; |dds_sin|count[0]   ; |dds_sin|count[0]~57          ; cout0            ;
; |dds_sin|count[0]   ; |dds_sin|count[0]~57COUT1_95  ; cout1            ;
; |dds_sin|count[1]   ; |dds_sin|count[1]~61          ; cout0            ;
; |dds_sin|count[1]   ; |dds_sin|count[1]~61COUT1_97  ; cout1            ;
; |dds_sin|count[2]   ; |dds_sin|count[2]~65          ; cout0            ;
; |dds_sin|count[2]   ; |dds_sin|count[2]~65COUT1_99  ; cout1            ;
; |dds_sin|count[3]   ; |dds_sin|count[3]~69          ; cout0            ;
; |dds_sin|count[3]   ; |dds_sin|count[3]~69COUT1_100 ; cout1            ;
; |dds_sin|count[4]   ; |dds_sin|count[4]~73          ; cout             ;
; |dds_sin|count[5]   ; |dds_sin|count[5]~77COUT1_102 ; cout1            ;
; |dds_sin|count[6]   ; |dds_sin|count[6]~81COUT1_104 ; cout1            ;
; |dds_sin|amp        ; |dds_sin|amp                  ; combout          ;
; |dds_sin|amp_out[0] ; |dds_sin|amp_out[0]           ; padio            ;
; |dds_sin|amp_out[1] ; |dds_sin|amp_out[1]           ; padio            ;
; |dds_sin|amp_out[2] ; |dds_sin|amp_out[2]           ; padio            ;
; |dds_sin|amp_out[3] ; |dds_sin|amp_out[3]           ; padio            ;
; |dds_sin|amp_out[4] ; |dds_sin|amp_out[4]           ; padio            ;
; |dds_sin|amp_out[5] ; |dds_sin|amp_out[5]           ; padio            ;
; |dds_sin|amp_out[6] ; |dds_sin|amp_out[6]           ; padio            ;
; |dds_sin|amp_out[7] ; |dds_sin|amp_out[7]           ; padio            ;
+---------------------+-------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                                                         ; Output Port Name                                                                                                                                                                               ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |dds_sin|ddsout_rom~749                                                                                                                                                           ; |dds_sin|ddsout_rom~749                                                                                                                                                                        ; combout          ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]                 ; combout          ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]~COUT            ; cout0            ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]~COUTCOUT1_95    ; cout1            ;
; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]                                                           ; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]                                                                        ; regout           ;
; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]                                                           ; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]~123                                                                    ; cout             ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]                 ; combout          ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]~COUT            ; cout0            ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]~COUTCOUT1_93    ; cout1            ;
; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]                                                           ; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]                                                                        ; regout           ;
; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]                                                           ; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]~127                                                                    ; cout0            ;
; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]                                                           ; |dds_sin|eg4:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]~127COUT1_225                                                           ; cout1            ;
; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[4]    ; |dds_sin|eg4:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[4]                 ; combout          ;