vector_to_int.txt

改程序用VHDL编写 实现由8位二进制数转化成整数的功能

library ieee;
use ieee.std_logic_1164.all;

entity  vector_to_int is
port
(input:in std_logic_vector(7 downto 0);
 flag:out boolean;
 q:out integer);
end;

architecture behave of vector_to_int is
begin
process(input)
variable temp:integer:=0;
 tep:
begin
flag<=false;
 temp:= temp*2;
   if (input(i)='1')then
   temp:=temp+1;
  elsif(input(i)/='0') then
 flag<=true;
end loop;
q<=temp;
end process;
end ;