📄 key_scan.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity key_scan is
port ( CLK: in std_logic;
RESET: in std_logic;
KIN: in std_logic_vector (3 downto 0);
SCAN: out std_logic_vector (3 downto 0);
output: out std_logic_vector (3 downto 0);
EO: out std_logic_vector (5 downto 0);
DISPLAY: out std_logic_vector (7 downto 0)
);
end key_scan;
architecture key_scan_arch of key_scan is
type STATE_TYPE is (S0, S1, S2, S3);
signal Sreg: STATE_TYPE;
signal counter: std_logic_vector (3 downto 0);
signal CLK_DIV: std_logic;
signal K: std_logic_vector (15 downto 0);
begin
process (CLK) -- 分频
begin
if CLK 'event and CLK='1' then
if counter="1111" then
counter <= (others=>'0');
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_DIV <= not counter(3);
process (CLK_DIV, RESET) -- state machine
begin
if RESET = '0' then Sreg <= S0;
elsif CLK_DIV 'event and CLK_DIV='1' then
case Sreg is
when S0 => if KIN = "0001" then K <= "0000000000000001"; Sreg <= S0;
elsif KIN = "0010" then K <= "0000000000000010"; Sreg <= S0;
elsif KIN = "0100" then K <= "0000000000000100"; Sreg <= S0;
elsif KIN = "1000" then K <= "0000000000001000"; Sreg <= S0;
else KIN = "0000" then K <= (others=>'0'); Sreg <= S1;
end if;
when S1 => if KIN = "0001" then K <= "0000000000010000"; Sreg <= S1;
elsif KIN = "0010" then K <= "0000000000100000"; Sreg <= S1;
elsif KIN = "0100" then K <= "0000000001000000"; Sreg <= S1;
elsif KIN = "1000" then K <= "0000000010000000"; Sreg <= S1;
else KIN = "0000" then K <= (others=>'0'); Sreg <= S2;
end if;
when S2 => if KIN = "0001" then K <= "0000000100000000"; Sreg <= S2;
elsif KIN = "0010" then K <= "0000001000000000"; Sreg <= S2;
elsif KIN = "0100" then K <= "0000010000000000"; Sreg <= S2;
elsif KIN = "1000" then K <= "0000100000000000"; Sreg <= S2;
else KIN = "0000" then K <= (others=>'0'); Sreg <= S3;
end if;
when S3 => if KIN = "0001" then K <= "0001000000000000"; Sreg <= S3;
elsif KIN = "0010" then K <= "0010000000000000"; Sreg <= S3;
elsif KIN = "0100" then K <= "0100000000000000"; Sreg <= S3;
elsif KIN = "1000" then K <= "1000000000000000"; Sreg <= S3;
else KIN = "0000" then K <= (others=>'0'); Sreg <= S0;
end if;
when others => Sreg <= S0;
end case;
end if;
end process;
process (Sreg) -- output logic
begin
case Sreg is
when S0 => SCAN <= "0001";
when S1 => SCAN <= "0010";
when S2 => SCAN <= "0100";
when S3 => SCAN <= "1000";
when others => SCAN <= "0000";
end case;
end process;
process (K) -- seven
begin
case K is
when "0000000000000001" => DISPLAY <= "11111100"; -- 0
when "0000000000000010" => DISPLAY <= "01100000"; -- 1
when "0000000000000100" => DISPLAY <= "11011010"; -- 2
when "0000000000001000" => DISPLAY <= "11110010"; -- 3
when "0000000000010000" => DISPLAY <= "01100110"; -- 4
when "0000000000100000" => DISPLAY <= "10110110"; -- 5
when "0000000001000000" => DISPLAY <= "10111110"; -- 6
when "0000000010000000" => DISPLAY <= "11100000"; -- 7
when "0000000100000000" => DISPLAY <= "11111110"; -- 8
when "0000001000000000" => DISPLAY <= "11110110"; -- 9
when "0000010000000000" => DISPLAY <= "11101110"; -- A
when "0000100000000000" => DISPLAY <= "00111110"; -- B
when "0001000000000000" => DISPLAY <= "10011100"; -- C
when "0010000000000000" => DISPLAY <= "01111010"; -- D
when "0100000000000000" => DISPLAY <= "10011110"; -- E
when "1000000000000000" => DISPLAY <= "10001110"; -- F
when others => DISPLAY <= "11111111"; -- no key
end case;
end process;
output <= KIN;
EO <= "111110";
end key_scan_arch;
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