fir5_ssg_auto.vhd

5阶数字滤波器FIR5

--------------------------------------------------------------------------
--
--  next code generated by gen_VHD.m, 04-Dec-2006 13:56:15
--  FIR5:  list, 1, 1, 2, 1
--
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.OPCODES.all;


entity FIR5_SSG is
	generic ( NX_g    : positive := 16;
	          M_g     : positive := 15;
	          MUL_delay_g : Time :=  5 ns;
	          ALU_delay_g : Time :=  2 ns;
	          REG_delay_g : Time :=  2 ns );
	port (	clk   :  in std_logic;
			reset :  in std_logic;
			start :  in std_logic;
			c0 :  in std_logic_vector(NX_g-1 downto 0);
			c1 :  in std_logic_vector(NX_g-1 downto 0);
			c2 :  in std_logic_vector(NX_g-1 downto 0);
			c3 :  in std_logic_vector(NX_g-1 downto 0);
			c4 :  in std_logic_vector(NX_g-1 downto 0);
			c5 :  in std_logic_vector(NX_g-1 downto 0);
			i1 :  in std_logic_vector(NX_g-1 downto 0);
			i2 :  in std_logic_vector(NX_g-1 downto 0);
			i3 :  in std_logic_vector(NX_g-1 downto 0);
			i4 :  in std_logic_vector(NX_g-1 downto 0);
			i5 :  in std_logic_vector(NX_g-1 downto 0);
			i0 :  in std_logic_vector(NX_g-1 downto 0);
			o0 : out std_logic_vector(NX_g-1 downto 0);
			o1 : out std_logic_vector(NX_g-1 downto 0);
			o2 : out std_logic_vector(NX_g-1 downto 0);
			o3 : out std_logic_vector(NX_g-1 downto 0);
			o4 : out std_logic_vector(NX_g-1 downto 0);
			o5 : out std_logic_vector(NX_g-1 downto 0);
			done  : out std_logic;
			error : out std_logic
	);
end FIR5_SSG;


architecture FIR5_SSG_behavioral of FIR5_SSG is

	component MUL_R
	generic ( NX_g    : positive := 16;
	          M_g     : positive := 15;
	          MUL_delay_g : Time :=  5 ns;
	          REG_delay_g : Time :=  2 ns );
		port (
			reset    :  in std_logic;		-- asynchronous, active high;
			clk      :  in std_logic;
			clk_en   :  in std_logic;
			op1      :  in std_logic_vector(NX_g-1 downto 0);
			op2      :  in std_logic_vector(NX_g-1 downto 0);
			result   : out std_logic_vector(NX_g-1 downto 0)
		);
	end component;

	component ALU_R
	generic ( NX_g    : positive := 16;
	          ALU_delay_g : Time :=  2 ns;
	          REG_delay_g : Time :=  2 ns );
		port (
			reset    :  in std_logic;		-- asynchronous, active high;
			clk      :  in std_logic;
			clk_en   :  in std_logic;
			opcode   : OPCODE_TYPE;
			op1      :  in std_logic_vector(NX_g-1 downto 0);
			op2      :  in std_logic_vector(NX_g-1 downto 0);
			result   : out std_logic_vector(NX_g-1 downto 0);
			overflow : out std_logic
		);
	end component;

	component REG_R
	generic ( NX_g    : positive := 16;
	          REG_delay_g : Time :=  2 ns );
		port (
			reset    :  in std_logic;		-- asynchronous, active high;
			clk      :  in std_logic;
			clk_en   :  in std_logic;
			D        :  in std_logic_vector(NX_g-1 downto 0);
			Q        : out std_logic_vector(NX_g-1 downto 0)
		);
	end component;

	type  STATE_TYPE is ( STATE_1, STATE_2, STATE_3, STATE_4, STATE_5,
	                      STATE_6, STATE_DONE );

	signal  CURRENT_STATE, NEXT_STATE : STATE_TYPE;
	signal  mul_1_cle_s : std_logic;
	signal  mul_1_in1_s, mul_1_in2_s, mul_1_out_r : std_logic_vector(NX_g-1 downto 0);
	signal  mul_2_cle_s : std_logic;
	signal  mul_2_in1_s, mul_2_in2_s, mul_2_out_r : std_logic_vector(NX_g-1 downto 0);
	signal  alu_1_cle_s, alu_1_err_r : std_logic;
	signal  alu_1_opc_s : OPCODE_TYPE;
	signal  alu_1_in1_s, alu_1_in2_s, alu_1_out_r : std_logic_vector(NX_g-1 downto 0);
	signal  reg_1_cle_s : std_logic;
	signal  reg_1_in_s, reg_1_out_r : std_logic_vector(NX_g-1 downto 0);
	signal  reg_2_cle_s : std_logic;
	signal  reg_2_in_s, reg_2_out_r : std_logic_vector(NX_g-1 downto 0);
	signal  started_s   : std_logic;
	signal  done_s      : std_logic;
	signal  err_check_s : std_logic;

begin

	-- Needed resources according to given scheduling method

	MUL_1: MUL_R generic map ( NX_g, M_g, MUL_delay_g, REG_delay_g )
				port map ( reset => reset,
				           clk => clk, clk_en => mul_1_cle_s,
				           op1 => mul_1_in1_s, op2 => mul_1_in2_s,
				           result => mul_1_out_r );

	MUL_2: MUL_R generic map ( NX_g, M_g, MUL_delay_g, REG_delay_g )
				port map ( reset => reset,
				           clk => clk, clk_en => mul_2_cle_s,
				           op1 => mul_2_in1_s, op2 => mul_2_in2_s,
				           result => mul_2_out_r );

	ALU_1  : ALU_R generic map ( NX_g , ALU_delay_g, REG_delay_g )
				port map ( reset => reset,
				           clk => clk, clk_en => alu_1_cle_s,
				           opcode => alu_1_opc_s,
				           op1 => alu_1_in1_s, op2 => alu_1_in2_s,
				           result => alu_1_out_r, overflow => alu_1_err_r );

	REG_1: REG_R generic map ( NX_g, REG_delay_g )
				port map ( reset => reset,
				           clk => clk, clk_en => reg_1_cle_s,
				           D => reg_1_in_s, Q => reg_1_out_r );

	REG_2: REG_R generic map ( NX_g, REG_delay_g )
				port map ( reset => reset,
				           clk => clk, clk_en => reg_2_cle_s,
				           D => reg_2_in_s, Q => reg_2_out_r );

------ controller code starts here ------

	STATES:	process( CURRENT_STATE,
				c0, c1, c2, c3, c4, c5, 
				i1, i2, i3, i4, i5, i0, 
				mul_1_out_r, mul_2_out_r, 
				alu_1_out_r, 
				alu_1_err_r,
				reg_1_out_r, reg_2_out_r )
			begin
			case CURRENT_STATE is
				when STATE_1 =>
					-- v0
					mul_1_in1_s <= c0;
					mul_1_in2_s <= i0;
					mul_1_cle_s <= '1';
					-- v1
					mul_2_in1_s <= c1;
					mul_2_in2_s <= i1;
					mul_2_cle_s <= '1';
					-- unused ALU
					alu_1_in1_s <= mul_1_out_r;  -- v0
					alu_1_in2_s <= mul_2_out_r;  -- v1
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '0';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s1
					reg_1_cle_s <= '0';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '0';
					--
					err_check_s <= '0';
					done_s      <= '0';
					NEXT_STATE  <= STATE_2;
				when STATE_2 =>
					-- v2
					mul_1_in1_s <= c2;
					mul_1_in2_s <= i2;
					mul_1_cle_s <= '1';
					-- v3
					mul_2_in1_s <= c3;
					mul_2_in2_s <= i3;
					mul_2_cle_s <= '1';
					-- s1
					alu_1_in1_s <= mul_1_out_r;  -- v0
					alu_1_in2_s <= mul_2_out_r;  -- v1
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '1';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s1
					reg_1_cle_s <= '0';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '0';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '0';
					NEXT_STATE  <= STATE_3;
				when STATE_3 =>
					-- v4
					mul_1_in1_s <= c4;
					mul_1_in2_s <= i4;
					mul_1_cle_s <= '1';
					-- v5
					mul_2_in1_s <= c5;
					mul_2_in2_s <= i5;
					mul_2_cle_s <= '1';
					-- s2
					alu_1_in1_s <= mul_1_out_r;  -- v2
					alu_1_in2_s <= mul_2_out_r;  -- v3
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '1';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s1
					reg_1_cle_s <= '1';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '0';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '0';
					NEXT_STATE  <= STATE_4;
				when STATE_4 =>
					-- unused multiplier
					mul_1_in1_s <= c4;
					mul_1_in2_s <= i4;
					mul_1_cle_s <= '0';
					-- unused multiplier
					mul_2_in1_s <= c5;
					mul_2_in2_s <= i5;
					mul_2_cle_s <= '0';
					-- s3
					alu_1_in1_s <= mul_1_out_r;  -- v4
					alu_1_in2_s <= mul_2_out_r;  -- v5
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '1';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s1
					reg_1_cle_s <= '0';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '1';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '0';
					NEXT_STATE  <= STATE_5;
				when STATE_5 =>
					-- unused multiplier
					mul_1_in1_s <= c4;
					mul_1_in2_s <= i4;
					mul_1_cle_s <= '0';
					-- unused multiplier
					mul_2_in1_s <= c5;
					mul_2_in2_s <= i5;
					mul_2_cle_s <= '0';
					-- s4
					alu_1_in1_s <= reg_1_out_r;  -- s1
					alu_1_in2_s <= reg_2_out_r;  -- s2
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '1';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s3
					reg_1_cle_s <= '1';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '1';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '0';
					NEXT_STATE  <= STATE_6;
				when STATE_6 =>
					-- unused multiplier
					mul_1_in1_s <= c4;
					mul_1_in2_s <= i4;
					mul_1_cle_s <= '0';
					-- unused multiplier
					mul_2_in1_s <= c5;
					mul_2_in2_s <= i5;
					mul_2_cle_s <= '0';
					-- s5
					alu_1_in1_s <= alu_1_out_r;  -- s4
					alu_1_in2_s <= reg_1_out_r;  -- s3
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '1';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s3
					reg_1_cle_s <= '1';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '0';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '0';
					NEXT_STATE  <= STATE_DONE;
				when STATE_DONE =>
					-- unused multiplier
					mul_1_in1_s <= c4;
					mul_1_in2_s <= i4;
					mul_1_cle_s <= '0';
					-- unused multiplier
					mul_2_in1_s <= c5;
					mul_2_in2_s <= i5;
					mul_2_cle_s <= '0';
					-- s5
					alu_1_in1_s <= alu_1_out_r;  -- s4
					alu_1_in2_s <= reg_1_out_r;  -- s3
					alu_1_opc_s <= OP_ADD;
					alu_1_cle_s <= '0';
					-- register(s)
					reg_1_in_s  <= alu_1_out_r;  -- s3
					reg_1_cle_s <= '0';
					reg_2_in_s  <= alu_1_out_r;  -- s2
					reg_2_cle_s <= '0';
					--
					err_check_s <= alu_1_err_r;
					done_s      <= '1';
					NEXT_STATE  <= STATE_DONE;
				when others =>
					NEXT_STATE  <= STATE_DONE;
					NULL;
			end case;
		end process STATES;

	MAIN:	process(clk,reset,start)
			begin
				if (clk'event AND clk = '1') then
					if (reset = '1' OR start = '1') then
						if (start = '1') then
							if (started_s = '0') then
								CURRENT_STATE <= STATE_1;
								started_s     <= '1';
							else
								CURRENT_STATE <= NEXT_STATE;
							end if;
						else
							CURRENT_STATE <= STATE_DONE;
							started_s     <= '0';
						end if;
					else
						CURRENT_STATE <= NEXT_STATE;
						started_s     <= '0';
					end if;
				end if;
			end process MAIN;

	-- connect feedthrough signal(s)
	o0 <= i0;
	o1 <= i1;
	o2 <= i2;
	o3 <= i3;
	o4 <= i4;
	-- connect status signal(s)
	done  <= done_s;
	error <= err_check_s AND not(reset);

	-- connect entity output(s) to resource(s)
	o5 <= alu_1_out_r;

------ end of controller code ------

end FIR5_SSG_behavioral;

-- [EOF]