testbench_fir5_auto.vhd

5阶数字滤波器FIR5

--------------------------------------------------------------------------
--
--  next code generated by gen_VHD.m, 04-Dec-2006 13:56:15
--  FIR5:  list, 1, 1, 2, 1
--
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use work.txt_util2.all;

entity testbench_FIR5 is
	generic ( N_g     : positive := 17;
	          M_g     : positive := 15;
	          NX_g    : positive := 17;
	          MUL_delay_g : Time := 5 ns;
	          ALU_delay_g : Time := 2 ns;
	          REG_delay_g : Time := 2 ns );
	port (
	       Error : out std_logic
	);
end testbench_FIR5;


architecture testbench of testbench_FIR5 is

	component FIR5
		generic ( N_g     : positive := 17;
		          M_g     : positive := 15;
		          NX_g    : positive := 17;
		          MUL_delay_g : Time := 5 ns;
		          ALU_delay_g : Time := 2 ns;
		          REG_delay_g : Time := 2 ns );
		port (
			Clk   :  in std_logic;
			Reset :  in std_logic;
			Start :  in std_logic;
			C0 :  in std_logic_vector(N_g-1 downto 0);
			C1 :  in std_logic_vector(N_g-1 downto 0);
			C2 :  in std_logic_vector(N_g-1 downto 0);
			C3 :  in std_logic_vector(N_g-1 downto 0);
			C4 :  in std_logic_vector(N_g-1 downto 0);
			C5 :  in std_logic_vector(N_g-1 downto 0);
			I0 :  in std_logic_vector(N_g-1 downto 0);
			O5 : out std_logic_vector(N_g-1 downto 0);
			Done  : out std_logic;
			Error : out std_logic
		);
	end component;

	signal C0_s : std_logic_vector(N_g-1 downto 0);
	signal C1_s : std_logic_vector(N_g-1 downto 0);
	signal C2_s : std_logic_vector(N_g-1 downto 0);
	signal C3_s : std_logic_vector(N_g-1 downto 0);
	signal C4_s : std_logic_vector(N_g-1 downto 0);
	signal C5_s : std_logic_vector(N_g-1 downto 0);

	signal Clk_s        : std_logic := '1';
	signal Nxt_InData_s : std_logic := '0';
	signal Reset_s      : std_logic := '0';

	signal I0_s : std_logic_vector(N_g-1 downto 0) := (others => '0');
	signal O5_s : std_logic_vector(N_g-1 downto 0);

	signal Done_s       : std_logic;

	file   inputs_file  : text open  read_mode is "FIR5.INP";
	file   output_file  : text open write_mode is "FIR5.OUT";

begin

	Clk_s <= not Clk_s  after 25 ns;

	FIR5_Lbl:
		FIR5
			generic map ( N_g, M_g, NX_g, MUL_delay_g, ALU_delay_g, REG_delay_g )
			port map (
				Clk   => Clk_s,
				Reset => Reset_s,
				Start => Nxt_InData_s,
				C0  => C0_s,
				C1  => C1_s,
				C2  => C2_s,
				C3  => C3_s,
				C4  => C4_s,
				C5  => C5_s,
				I0  => I0_s,
				O5  => O5_s,
				Done  => Done_s,
				Error => Error
			);

	FILE_READ_Cx:
		-- read constants from .inp-file (vhdl-hex format)
		process(Clk_s,Reset_s)
			variable str_v : string(1 to 80);
			variable tmp_v : std_logic_vector(19 downto 0);
		begin
			if (Clk_s'event AND Clk_s = '1') then
				if (Reset_s = '1') then
					print("[e-mail]: start");
					-- skip line if starting with a '-'
					str_read(inputs_file, str_v);
					print( "str = " & str_v );
					while str_v(1 to 2) = "--" loop
						str_read(inputs_file, str_v);
					end loop;
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C0_s <= tmp_v(N_g-1 downto 0);
					str_read(inputs_file, str_v);
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C1_s <= tmp_v(N_g-1 downto 0);
					str_read(inputs_file, str_v);
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C2_s <= tmp_v(N_g-1 downto 0);
					str_read(inputs_file, str_v);
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C3_s <= tmp_v(N_g-1 downto 0);
					str_read(inputs_file, str_v);
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C4_s <= tmp_v(N_g-1 downto 0);
					str_read(inputs_file, str_v);
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					C5_s <= tmp_v(N_g-1 downto 0);
				end if;
			end if;
		end process FILE_READ_Cx;

	FILE_READ_INPUTs:
		-- read sample values from .inp-file at rising edge of Nxt_InData_s
		process(Nxt_InData_s)
			variable str_v : string(1 to 80);
			variable tmp_v : std_logic_vector(19 downto 0);
		begin
			if (Nxt_InData_s'event AND Nxt_InData_s = '1') then
				if not endfile(inputs_file) then
					-- skip line if starting with a '-'
					str_read(inputs_file, str_v);
					print( "str = " & str_v );
					while str_v(1 to 2) = "--" loop
						str_read(inputs_file, str_v);
					end loop;
					tmp_v := hex_string_to_slv(str_v(3 to 7));
					I0_s <= tmp_v(N_g-1 downto 0);
					print("[e-mail]: read I0_s");
				else
					print("[e-mail]: reached end of file ...");
				end if;
			end if;
		end process FILE_READ_INPUTs;

	FILE_WRITE_OUTPUTs:
		-- write output values to .out-file at falling edge of Done_s
		process(Done_s)
			variable count_v : integer := 0;
		begin
			if (Done_s'event AND Done_s = '0') then
				if (count_v /= 0) then
					print(output_file, "x""" & hstr(O5_s) & """");
				end if;
				count_v := 1;
			end if;
		end process FILE_WRITE_OUTPUTs;

	STIMULUS_Lbl:
		process
		begin
			print(output_file, "-- VHDL testbench output:");
			print(output_file, "-- Format [17 15 (0)]");
			print(output_file, "-- Output: o5");
			wait for  15 ns;  Reset_s  <= '1';
			wait for  50 ns;  Reset_s  <= '0';
			wait for  15 ns;  Nxt_InData_s <= '1';
			wait for 150 ns;  Nxt_InData_s <= '0';
		LOOP_Lbl:
			while not endfile(inputs_file) loop
				wait until Done_s = '1';
				wait for  90 ns;  Nxt_InData_s <= '1';
				wait for 150 ns;  Nxt_InData_s <= '0';
			end loop LOOP_Lbl;
			-- finish writing last output value
			wait until Done_s = '1';
			wait for 90 ns;  Nxt_InData_s <= '1';

			wait;
		end process STIMULUS_Lbl;

end testbench;

-- [EOF]