fir5.vhd

5阶数字滤波器FIR5

--------------------------------------------------------------------------
--
--  next code generated by gen_VHD.m, 04-Dec-2006 13:56:15
--  FIR5:  list, 1, 1, 2, 1
--
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;


entity FIR5 is
	generic ( N_g     : positive := 17;
	          M_g     : positive := 15;
	          NX_g    : positive := 17;
	          MUL_delay_g : Time := 5 ns;
	          ALU_delay_g : Time := 2 ns;
	          REG_delay_g : Time := 2 ns);
	port (	Clk   :  in std_logic;
			Reset :  in std_logic;
			Start :  in std_logic;
			C0 :  in std_logic_vector(N_g-1 downto 0);
			C1 :  in std_logic_vector(N_g-1 downto 0);
			C2 :  in std_logic_vector(N_g-1 downto 0);
			C3 :  in std_logic_vector(N_g-1 downto 0);
			C4 :  in std_logic_vector(N_g-1 downto 0);
			C5 :  in std_logic_vector(N_g-1 downto 0);
			I0 :  in std_logic_vector(N_g-1 downto 0);
			O5 : out std_logic_vector(N_g-1 downto 0);
			Done  : out std_logic;
			Error : out std_logic
	);
end FIR5;


architecture FIR5_behavioral of FIR5 is

	component FIR5_SSG
	generic ( NX_g    : positive := 16;
	          M_g     : positive := 15;
	          MUL_delay_g : Time :=  5 ns;
	          ALU_delay_g : Time :=  2 ns;
	          REG_delay_g : Time :=  2 ns );
		port (
			clk   :  in std_logic;
			reset :  in std_logic;
			start :  in std_logic;
			c0 :  in std_logic_vector(NX_g-1 downto 0);
			c1 :  in std_logic_vector(NX_g-1 downto 0);
			c2 :  in std_logic_vector(NX_g-1 downto 0);
			c3 :  in std_logic_vector(NX_g-1 downto 0);
			c4 :  in std_logic_vector(NX_g-1 downto 0);
			c5 :  in std_logic_vector(NX_g-1 downto 0);
			i1 :  in std_logic_vector(NX_g-1 downto 0);
			i2 :  in std_logic_vector(NX_g-1 downto 0);
			i3 :  in std_logic_vector(NX_g-1 downto 0);
			i4 :  in std_logic_vector(NX_g-1 downto 0);
			i5 :  in std_logic_vector(NX_g-1 downto 0);
			i0 :  in std_logic_vector(NX_g-1 downto 0);
			o0 : out std_logic_vector(NX_g-1 downto 0);
			o1 : out std_logic_vector(NX_g-1 downto 0);
			o2 : out std_logic_vector(NX_g-1 downto 0);
			o3 : out std_logic_vector(NX_g-1 downto 0);
			o4 : out std_logic_vector(NX_g-1 downto 0);
			o5 : out std_logic_vector(NX_g-1 downto 0);
			done  : out std_logic;
			error : out std_logic
		);
	end component;

	signal c0_s : std_logic_vector(NX_g-1 downto 0);
	signal c1_s : std_logic_vector(NX_g-1 downto 0);
	signal c2_s : std_logic_vector(NX_g-1 downto 0);
	signal c3_s : std_logic_vector(NX_g-1 downto 0);
	signal c4_s : std_logic_vector(NX_g-1 downto 0);
	signal c5_s : std_logic_vector(NX_g-1 downto 0);

	signal i0_s, i0_r : std_logic_vector(N_g-1 downto 0);
	signal o5_s, o5_r : std_logic_vector(N_g-1 downto 0);

	signal i0_SSG_s : std_logic_vector(NX_g-1 downto 0);
	signal o5_SSG_s : std_logic_vector(NX_g-1 downto 0);

	-- delay elements
	signal o0_s, T_o0_r : std_logic_vector(NX_g-1 downto 0);
	signal o1_s, T_o1_r : std_logic_vector(NX_g-1 downto 0);
	signal o2_s, T_o2_r : std_logic_vector(NX_g-1 downto 0);
	signal o3_s, T_o3_r : std_logic_vector(NX_g-1 downto 0);
	signal o4_s, T_o4_r : std_logic_vector(NX_g-1 downto 0);

	signal done_s : std_logic;

begin

	i0_s <= I0;

	SIGN_EXTENT_Lbl:
		for i in NX_g-1 downto N_g generate
			c0_s(i) <= C0(N_g-1);
			c1_s(i) <= C1(N_g-1);
			c2_s(i) <= C2(N_g-1);
			c3_s(i) <= C3(N_g-1);
			c4_s(i) <= C4(N_g-1);
			c5_s(i) <= C5(N_g-1);

			i0_SSG_s(i) <= i0_r(N_g-1);
		end generate;
	c0_s(N_g-1 downto 0) <= C0;
	c1_s(N_g-1 downto 0) <= C1;
	c2_s(N_g-1 downto 0) <= C2;
	c3_s(N_g-1 downto 0) <= C3;
	c4_s(N_g-1 downto 0) <= C4;
	c5_s(N_g-1 downto 0) <= C5;

	i0_SSG_s(N_g-1 downto 0) <= i0_r;

	FIR5_SSG_Lbl:
		FIR5_SSG
			generic map ( NX_g, M_g, MUL_delay_g, ALU_delay_g, REG_delay_g	)
			port map (
				clk   => Clk,
				reset => Reset,
				start => Start,
				c0 => c0_s,
				c1 => c1_s,
				c2 => c2_s,
				c3 => c3_s,
				c4 => c4_s,
				c5 => c5_s,
				i0 => i0_SSG_s,
				i1 => T_o0_r,
				i2 => T_o1_r,
				i3 => T_o2_r,
				i4 => T_o3_r,
				i5 => T_o4_r,
				o0 => o0_s,
				o1 => o1_s,
				o2 => o2_s,
				o3 => o3_s,
				o4 => o4_s,
				o5 => o5_SSG_s,
				done  => done_s,
				error => Error
			);

	MAIN:
		process(Clk,Reset,done_s)
		begin
			if (Clk'event AND Clk = '1') then
				if (Reset = '1') then
					i0_r <= (others => '0');
					T_o0_r <= (others => '0');
					T_o1_r <= (others => '0');
					T_o2_r <= (others => '0');
					T_o3_r <= (others => '0');
					T_o4_r <= (others => '0');
					o5_r <= (others => '0');
				else
					if (done_s = '1' AND Start = '1') then
						i0_r <= i0_s;
						T_o0_r <= o0_s;
						T_o1_r <= o1_s;
						T_o2_r <= o2_s;
						T_o3_r <= o3_s;
						T_o4_r <= o4_s;
						o5_r <= o5_s;
					end if;
				end if;
			end if;
		end process MAIN;

	o5_s <= o5_SSG_s(N_g-1 downto 0);
	O5 <= o5_r;
	Done <= done_s;

end FIR5_behavioral;

-- [EOF]