resources_reg.vhd

5阶数字滤波器FIR5

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--  resources ALU_R, MUL_R and REG_R
--  (c) H.J. Lincklaen Arriens
--      Delft University of Technology, June 2005
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package OPCODES is
	type OPCODE_TYPE is (OP_ADD,OP_SUB);
	attribute ENUM_ENCODING	: STRING;
	attribute ENUM_ENCODING of OPCODE_TYPE	:
		type is "1 0";
end;

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-- adder/subtractor with registered (Clock-Enable and asynchronous Reset) output
-- Overflow detection using Method 3 as described in ProRisc 2002 article:
--    additional FA for bit N_g to convert msCarry into msSum
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.OPCODES.all;

entity ALU_R is
	generic( NX_g    : positive := 16;
			 M_g     : positive := 15;
			 ALU_delay_g : Time :=  2 ns;
			 REG_delay_g : Time :=  2 ns );

	port (
		reset	 :  in std_logic;		-- asynchronous, active high 
		clk		 :  in std_logic;
		clk_en   :  in std_logic;
		op1		 :  in std_logic_vector(NX_g-1 downto 0);
		op2		 :  in std_logic_vector(NX_g-1 downto 0);
		opcode	 : OPCODE_TYPE;
		result	 : out std_logic_vector(NX_g-1 downto 0); 
		overflow : out std_logic
    );
end ALU_R;

architecture arch_ALU_R of ALU_R is
    
	signal	op1_s, op2_s : std_logic_vector(NX_g downto 0);
	signal	tmp_s  	     : std_logic_vector(NX_g downto 0);
	signal 	result_s     : std_logic_vector(NX_g-1 downto 0);
	signal 	result_r     : std_logic_vector(NX_g-1 downto 0);
	signal 	positive_s   : std_logic;
	signal 	overflow_s   : std_logic;
	signal 	overflow_r   : std_logic;
	
begin

	
	op1_s 	   <= op1(NX_g-1) & op1;	-- sign extend op1
	op2_s 	   <= op2(NX_g-1) & op2;	-- sign extend op2
	positive_s <= not( tmp_s(NX_g) );
	result	   <= result_r;
	overflow   <= overflow_r;
	
	process(reset,clk,clk_en,opcode, op1_s,op2_s,tmp_s,positive_s)
	begin
		overflow_s  <= '0';
		case opcode is
    		when OP_ADD =>					--  add
       			tmp_s 	    <= op1_s + op2_s;
				result_s    <= tmp_s(NX_g-1 downto 0) after ALU_delay_g;
				overflow_s  <= not( positive_s xor tmp_s(NX_g-1) ); 
			when OP_SUB =>					--  sub
				tmp_s       <= op1_s - op2_s;
				result_s    <= tmp_s(NX_g-1 downto 0) after ALU_delay_g;
				overflow_s  <= not( positive_s xor tmp_s(NX_g-1) ); 
			when others	=>
				tmp_s	    <= (others => '0');
		end case;
		if (reset = '1') then
			result_r   <= (others => '0') after REG_delay_g;
			overflow_r <= '0' after REG_delay_g;
		else
			if (clk'event) and (clk = '1') then
				if (clk_en = '1') then
					result_r   <= result_s   after REG_delay_g;
					overflow_r <= overflow_s after REG_delay_g;
				end if;
			end if;
		end if;
	end	process;				

end arch_ALU_R;


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-- multiplier with registered (Clock-Enable and asynchronous Reset) output
-- for a Spartan 3 device, this all maps to one (or more) MUL18x18S component(s)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity MUL_R is
	generic( NX_g    : positive := 16;
			 M_g     : positive := 15;
			 MUL_delay_g : Time :=  5 ns;
			 REG_delay_g : Time :=  2 ns );
	port (
		reset	:  in std_logic;		-- asynchronous, active high 
		clk		:  in std_logic;
		clk_en  :  in std_logic;
		op1		:  in std_logic_vector(NX_g-1 downto 0);
		op2		:  in std_logic_vector(NX_g-1 downto 0);
		result	: out std_logic_vector(NX_g-1 downto 0)
	);
end MUL_R;

architecture arch_MUL_R of MUL_R is
    signal	tmp_s    : std_logic_vector(2*NX_g-1 downto 0);
begin

	process(reset,clk,clk_en,op1,op2)
	begin
		tmp_s  <= (op1 * op2) after MUL_delay_g;
		if (reset = '1') then
			result <= (others => '0') after REG_delay_g;
		else
			if (clk'event) and (clk = '1') then
				if (clk_en = '1') then
					result <= tmp_s( (NX_g + M_g -1) downto M_g) after REG_delay_g; 
				end if;
			end if;
		end if;
	end process;


end arch_MUL_R;


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-- register with Clock-Enable and asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity REG_R is
	generic( NX_g    : positive := 16;
			 M_g     : positive := 15;
			 REG_delay_g : Time :=  2 ns );
	port (
		reset	:  in std_logic;		-- asynchronous, active high  
		clk		:  in std_logic;
		clk_en  :  in std_logic;
		D		:  in std_logic_vector(NX_g-1 downto 0);
		Q		: out std_logic_vector(NX_g-1 downto 0)
	);
end REG_R;

architecture arch_REG_R of REG_R is
begin

	process(reset,clk,clk_en)
	begin
		if (reset = '1') then
			Q <= (others => '0') after REG_delay_g;
		else
			if (clk'event) and (clk = '1') then
				if (clk_en = '1') then
					Q <= D after REG_delay_g;
				end if;
			end if;
		end if;
	end process;

end arch_REG_R;