lcdp_fifo.v

液晶model 设计LCD 并口模式下的仿真model

module lcdp_fifo(

       clk,
       rst_n,

       fifo_rd,
       fifo_wr,
       fifo_cs,
       fifo_a0,
       
       fifo_da

);

`define    DATA_LENGTH        8 
`define    FIFO_LENGTH        256  //max write is 256 byte

input        clk     ;
input        rst_n   ;

input        fifo_rd ;
input        fifo_wr ;
input        fifo_cs ;
input        fifo_a0 ;
            
inout[`DATA_LENGTH-1:0]   fifo_da ; 

//---------------------------------------------------------------------------------------
//                   Reg Description
//---------------------------------------------------------------------------------------

reg  [`DATA_LENGTH-1:0]   ram_data [`FIFO_LENGTH-1 : 0];

integer      i ;
integer      da_wr_cnt = 0  ,     da_rd_cnt = 0  ;
             
wire  da_wr , da_rd ;             

//---------------------------------------------------------------------------------------
//                   Logic Description
//---------------------------------------------------------------------------------------


always@(negedge da_wr or negedge rst_n)
      if(~rst_n)begin
        da_wr_cnt <= 0 ;
        da_rd_cnt <= 0 ;
      end
      else if(~da_wr)begin
          $display(" Write 0x%h on %t, a0 is %d", fifo_da, $time, fifo_a0);
          da_wr_cnt <= da_wr_cnt + 1 ;
      end  

always@( negedge da_rd or negedge rst_n)
      if(~rst_n)begin
        da_rd_cnt <= 0 ;
      end
      else if(~da_rd)begin
        if(da_rd_cnt > da_wr_cnt )
          $display(" Read no data on %t", $time) ;
        else
          $display(" Read 0x%h on %t,  a0 is %d", fifo_da, $time, fifo_a0);
          da_rd_cnt <= da_rd_cnt + 1 ;
      end
      
// data storing
always@(negedge da_wr or negedge rst_n)
      if(~rst_n)begin
        for(i=0 ; i<`FIFO_LENGTH ; i=i+1)begin
          ram_data[i] <= 0 ;
        end
      end
      else if(~da_wr)begin
        ram_data[da_wr_cnt] <= fifo_da[`DATA_LENGTH-1:0] ;
      end

assign  da_wr = ~fifo_wr & ~fifo_cs ;
assign  da_rd = ~fifo_rd & ~fifo_cs ;

// data output

assign  fifo_da[`DATA_LENGTH-1:0] = da_rd ? ram_data[da_rd_cnt] : `DATA_LENGTH'bz ;

endmodule