decoder_rtl.vhd

电子设计培训

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY decoder IS
   PORT( 
      blockp  : IN     std_logic;
      channel : IN     std_logic;
      clk     : IN     std_logic;
      reset   : IN     std_logic;
      decblkp : OUT    std_logic;
      decode  : OUT    std_logic
   );

-- Declarations

END decoder ;

-- hds interface_end
library Hamming;
use Hamming.matrix.all;
ARCHITECTURE rtl OF decoder IS
	signal palcode : std_logic_vector(CODE_LENGTH-1 downto 0);
	signal syndrm : std_logic_vector(CHECK_LENGTH-1 downto 0);
	signal dec : std_logic_vector(SOURCE_LENGTH-1 downto 0);
	signal cnt : integer range 0 to CODE_LENGTH-1;
BEGIN
	s2p_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			palcode<=channel & palcode(palcode'HIGH downto 1);
		end if;
		if reset='1' then
			palcode<=(others=>'0');
		end if;
	end process;

	dec_proc: process(palcode)
		variable v : std_logic;
	begin
		for i in 0 to CHECK_LENGTH-1 loop
			v:='0';
			for j in 0 to CODE_LENGTH-1 loop
				v:=v xor (H(i,j) and palcode(j));
			end loop;
			syndrm(i)<=v;
		end loop;			
	end process;

	p2s_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			if cnt=0 then
				dec<=palcode(SOURCE_LENGTH-1 downto 0) xor C(CONV_INTEGER(syndrm));
			else
				dec<='0'&dec(dec'HIGH downto 1);
			end if;
		end if;
		if reset='1' then
			dec<=(others=>'0');
		end if;
	end process;
	decode<=dec(0);

	ctrl_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			if cnt=CODE_LENGTH-1 then
				cnt<=0;
			else
				cnt<=cnt+1;
			end if;
			if blockp='1' then
				cnt<=1;
			end if;
			decblkp<='0';
			if cnt=0 then
				decblkp<='1';
			end if;
		end if;
		if reset='1' then
			cnt<=0;
		end if;
	end process;
END rtl;