testbench_struct.vhd

电子设计培训

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY testbench IS
-- Declarations

END testbench ;

-- hds interface_end
--
-- VHDL Architecture Hamming.testbench.struct
--
-- Created:
--          by - gening.UNKNOWN (KF185)
--          at - 14:54:24 03/17/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


LIBRARY Hamming;

ARCHITECTURE struct OF testbench IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL blockp  : std_logic;
   SIGNAL channel : std_logic;
   SIGNAL clk     : std_logic;
   SIGNAL decblkp : std_logic;
   SIGNAL decode  : std_logic;
   SIGNAL encode  : std_logic;
   SIGNAL err     : std_logic;
   SIGNAL reset   : std_logic;
   SIGNAL source  : std_logic;
   SIGNAL srcblkp : std_logic;


   -- Component Declarations
   COMPONENT decoder
   PORT (
      blockp  : IN     std_logic ;
      channel : IN     std_logic ;
      clk     : IN     std_logic ;
      reset   : IN     std_logic ;
      decblkp : OUT    std_logic ;
      decode  : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT encoder
   PORT (
      clk     : IN     std_logic ;
      reset   : IN     std_logic ;
      source  : IN     std_logic ;
      srcblkp : IN     std_logic ;
      blockp  : OUT    std_logic ;
      encode  : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT genchk
   PORT (
      decblkp : IN     std_logic ;
      decode  : IN     std_logic ;
      encode  : IN     std_logic ;
      channel : OUT    std_logic ;
      clk     : OUT    std_logic ;
      err     : OUT    std_logic ;
      reset   : OUT    std_logic ;
      source  : OUT    std_logic ;
      srcblkp : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : decoder USE ENTITY Hamming.decoder;
   FOR ALL : encoder USE ENTITY Hamming.encoder;
   FOR ALL : genchk USE ENTITY Hamming.genchk;
   -- pragma synthesis_on


BEGIN
   -- Instance port mappings.
   I1 : decoder
      PORT MAP (
         blockp  => blockp,
         channel => channel,
         clk     => clk,
         reset   => reset,
         decblkp => decblkp,
         decode  => decode
      );
   I0 : encoder
      PORT MAP (
         clk     => clk,
         reset   => reset,
         source  => source,
         srcblkp => srcblkp,
         blockp  => blockp,
         encode  => encode
      );
   I2 : genchk
      PORT MAP (
         decblkp => decblkp,
         decode  => decode,
         encode  => encode,
         channel => channel,
         clk     => clk,
         err     => err,
         reset   => reset,
         source  => source,
         srcblkp => srcblkp
      );

END struct;