genchk_behavioral.vhd

电子设计培训

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY genchk IS
   PORT( 
      decblkp : IN     std_logic;
      decode  : IN     std_logic;
      encode  : IN     std_logic;
      channel : OUT    std_logic;
      clk     : OUT    std_logic;
      err     : OUT    std_logic;
      reset   : OUT    std_logic;
      source  : OUT    std_logic;
      srcblkp : OUT    std_logic
   );

-- Declarations

END genchk ;

-- hds interface_end
library IEEE;
use IEEE.math_real.all;
ARCHITECTURE behavioral OF genchk IS
	signal clki,clk1, sourcei : std_logic :='0';
	signal noise : std_logic :='0';
	signal save : std_logic_vector(7*3-1 downto 0);
	signal cnt : integer range 0 to 6;
	signal decpos : integer  :=0;
BEGIN
	reset<='1','0' after 150 ns;
	clki<=not clki after 50 ns;
	clk<=clki;
	clk1<=clki;

	channel<=(encode xor noise) after 1 ns;
	noise_proc: process(clk1)
		variable seed1, seed2 : positive :=45;
		variable x : real;
	begin
		if rising_edge(clk1) then
			UNIFORM(seed1,seed2,x);
			noise<='0';
			if (x<0.005) then
				noise<='1';
			end if;
		end if;
	end process;

	source<=sourcei;
	src_proc: process(clk1)
		variable seed1, seed2 : positive :=2;
		variable x : real;
	begin
		if rising_edge(clk1) then
			if cnt=6 or cnt<3 then
				UNIFORM(seed1,seed2,x);
				if (x>0.5) then
					sourcei<='1';
				else
					sourcei<='0';
				end if;
			else
				sourcei<='0';
			end if;
			save<=save(save'HIGH-1 downto 0) & sourcei;
		end if;
	end process;

	chk_proc: process(clk1)
	begin
		if rising_edge(clk1) then
			err<='0';
			if cnt>=0 and cnt<=3 then
				if save(decpos)/=decode  then
					err<='1';
				end if;
			end if;
		end if;
	end process;

	ctrl_proc: process(clk1)
	begin
		if rising_edge(clk1) then
			if cnt=6 then
				cnt<=0;
			else
				cnt<=cnt+1;
			end if;
			srcblkp<='0';
			if cnt=6 then
				srcblkp<='1';
			end if;
			if decblkp='1' then
				decpos<=7+cnt-1;
			end if;
		end if;
	end process;
END behavioral;