encoder_rtl.vhd

电子设计培训

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY encoder IS
   PORT( 
      clk     : IN     std_logic;
      reset   : IN     std_logic;
      source  : IN     std_logic;
      srcblkp : IN     std_logic;
      blockp  : OUT    std_logic;
      encode  : OUT    std_logic
   );

-- Declarations

END encoder ;

-- hds interface_end
library Hamming;
use Hamming.matrix.all;
ARCHITECTURE rtl OF encoder IS
	-- serial to parallel registers
	signal srccode : std_logic_vector(SOURCE_LENGTH-1 downto 0);
	-- matrix calcute result
	signal enccom : std_logic_vector(CODE_LENGTH-1 downto 0);
	-- parallel to serial registers
	signal encreg : std_logic_vector(CODE_LENGTH-1 downto 0);
	-- cnt is a counter, acting as a controller
	signal cnt : integer range 0 to CODE_LENGTH-1;
BEGIN
	s2p: process(clk,reset)
	begin
		if rising_edge(clk) then
			srccode<=source & srccode(srccode'HIGH downto 1);
		end if;
		if reset='1' then
			srccode<=(others=>'0');
		end if;
	end process;

	encode_proc: process(srccode)
		variable v : std_logic;
	begin
		for j in 0 to CODE_LENGTH-1 loop
			v:='0';
			for i in 0 to SOURCE_LENGTH-1 loop
				v:=v xor ( srccode(i) and G(i,j));
			end loop;		
			enccom(j)<=v;
		end loop;
	end process;

	p2s_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			-- load
			if cnt=SOURCE_LENGTH then 
				encreg<=enccom;
				blockp<='1';
			else
			-- serial out
				encreg<='0' &encreg(CODE_LENGTH-1 downto 1);
				blockp<='0';
			end if;
		end if;
		if reset='1' then
			encreg<=(others=>'0');
			blockp<='0';
		end if;	
	
	end process;


	encode<=encreg(0);

	ctrl_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			if (cnt=CODE_LENGTH-1) then
				cnt<=0;
			else
				cnt<=cnt+1;
			end if;
			-- cnt synchronized with srcblkp cnt=0 is aligned with srcblkp pulse
			if srcblkp='1' then
				cnt<=1;
			end if;
		end if;
		if reset='1' then
			cnt<=0;
		end if;
	end process;
END rtl;