counter6.tan.rpt

简易数字钟： 采用分成次设计

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                      ; To                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 86.96 MHz ( period = 11.499 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst1|f74161:sub|99                 ; CLK        ; CLK      ; None                        ; None                      ; 11.238 ns               ;
; N/A                                     ; 90.44 MHz ( period = 11.057 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst1|f74161:sub|110                ; CLK        ; CLK      ; None                        ; None                      ; 10.796 ns               ;
; N/A                                     ; 90.60 MHz ( period = 11.037 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst1|f74161:sub|87                 ; CLK        ; CLK      ; None                        ; None                      ; 10.776 ns               ;
; N/A                                     ; 90.86 MHz ( period = 11.006 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst5|f74161:sub|9                  ; CLK        ; CLK      ; None                        ; None                      ; 10.745 ns               ;
; N/A                                     ; 90.87 MHz ( period = 11.005 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst5|f74161:sub|110                ; CLK        ; CLK      ; None                        ; None                      ; 10.744 ns               ;
; N/A                                     ; 92.96 MHz ( period = 10.757 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst1|f74161:sub|9                  ; CLK        ; CLK      ; None                        ; None                      ; 10.496 ns               ;
; N/A                                     ; 93.08 MHz ( period = 10.743 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst5|f74161:sub|99                 ; CLK        ; CLK      ; None                        ; None                      ; 10.482 ns               ;
; N/A                                     ; 96.74 MHz ( period = 10.337 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter60:inst1|counter6:inst|74161:inst|f74161:sub|99    ; CLK        ; CLK      ; None                        ; None                      ; 10.076 ns               ;
; N/A                                     ; 96.96 MHz ( period = 10.313 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter24:inst2|74161:inst5|f74161:sub|87                 ; CLK        ; CLK      ; None                        ; None                      ; 10.052 ns               ;
; N/A                                     ; 98.01 MHz ( period = 10.203 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|110  ; counter24:inst2|74161:inst1|f74161:sub|99                 ; CLK        ; CLK      ; None                        ; None                      ; 9.942 ns                ;
; N/A                                     ; 98.62 MHz ( period = 10.140 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter60:inst1|counter6:inst|74161:inst|f74161:sub|110   ; CLK        ; CLK      ; None                        ; None                      ; 9.879 ns                ;
; N/A                                     ; 99.11 MHz ( period = 10.090 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|9    ; counter60:inst1|counter10:inst1|74161:inst|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 9.829 ns                ;
; N/A                                     ; 102.45 MHz ( period = 9.761 ns )                    ; counter60:inst|counter10:inst1|74161:inst|f74161:sub|110  ; counter24:inst2|74161:inst1|f74161:sub|110                ; CLK        ; CLK      ; None                        ; None                      ; 9.500 ns                ;